Abstract: A system for charging a battery of an energy storage system using a photovoltaic inverter, includes: a photovoltaic inverter configured to convert a DC power generated from a photovoltaic module into an AC power, and to output the AC power; and an energy storage system configured to set a preset power value by considering an output power of the photovoltaic inverter according to the amount of solar radiation, and configured to charge a battery in a mode selected from a constant current (CC) mode and a constant voltage (CV) mode based on a comparison result obtained by comparing the preset power value, with an input power generated from the photovoltaic module and input from the photovoltaic inverter.

Abstract: A data processing system includes a number of processor cores each having a trace interface with an address signal carrying program addresses being executed, a processor core identification circuit connected to the trace interfaces and operable to replace a portion of some of the program addresses with a processor core identification that identifies which of the processor cores provided the program addresses, and an execution trace buffer operable to store the program addresses associated with non-sequential execution in the processor cores. At least some of the program addresses include the processor core identification along with address bits.

Abstract: A system is described that analyzes timing of a design and conditionally replaces values of a cell to lower total power within circuit paths having a positive timing margin. The system includes a computing device that includes a memory for storing modules and a processor that is operable to execute the modules. The modules cause the processor to conditionally replace a first semiconductor characteristic with a second semiconductor characteristic associated with a cell in a path of a circuit design and estimating a delay and a slack of the path based upon the first semiconductor characteristic. The modules also cause the processor to determine whether the second semiconductor characteristic causes a timing violation with respect to the path and causes conditional replacement of the second semiconductor characteristic with a third semiconductor characteristic until the timing violation is removed.

Abstract: The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing. To prevent buffer overflow or degraded decoder performance, the memory availability of the buffer is monitored, and transfers are suspended when the memory availability of the buffer is below a threshold buffer availability.

Abstract: Methods and systems for reducing memory test time utilizing a serial per march element communicating architecture. A small number of slow speed signals can be configured between a BIST wrapper and a BIST controller to transfer information in accordance with a BIST sequence that includes a number of march elements. An information transfer protocol can be implemented between the BIST wrapper and the BIST controller to transfer Information with respect to each march element that includes a number of BIST operations, address sequencing information, and data pattern. A command register can be loaded utilizing the slow speed signals and slow speed clock and content of the command register can be decoded. An encoded BIST operation can then be executed once for each BIST operation per march element. The serial per march element communicating architecture reduces test time as a communication overhead and a requirement for high speed wires are eliminated.

Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and first openings in the photoresist are formed. Metal layers are formed by electroplating metal into the first openings for a first time period. Then the photoresist is patterned to form second openings having a smaller diameter than the first openings. Narrow pillars are formed by electroplating metal into the second openings for a second time period during which the metal is also added to the metal layers in the first openings to form wide pillars having substantially the same height as the narrow pillars. The photoresist is then removed along with conductive layers on the device used as part of the plating process.

Abstract: A printed circuit board (PCB) for reducing EMI of an electric vehicle is provided. The PCB includes an electromagnetic interference (EMI) filter connected to a battery power supply and filtering EMI noise, a plurality of chassis ground (GND) terminals, a chassis GND pattern formed to ground a power GND terminal to the plurality of chassis GND terminals, a coupling prevention capacitor installed between the power GND terminal and the plurality of chassis GND terminals to prevent noise coupling between the power GND terminal and the chassis GND terminals, and a merge resistor installed between the power GND terminal and the plurality of chassis GND terminals to merge noise occurring when charging the battery power supply to the plurality of chassis GND terminals.

Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first photoresist covers the pillars of the first diameter. Openings of a second diameter are formed in the first and second photoresists to expose a second set of die pads. Pillars of the second diameter are formed by electroplating metal onto the exposed die pads. The photoresists are then removed along with conductive layers on the device used as part of the plating process.

Abstract: A surgical clamp jaw is disclosed, having an inner profile and a deflection control profile opposite the inner profile. In one embodiment, the inner profile has a first substantially concave profile in an unclamped position and a second substantially flat profile in a clamped position. In one embodiment, the deflection control profile has one or more sets of corresponding abutment surfaces, at least one set of which is not contacting each other when the inner profile is in the unclamped position and which is contacting each other when the inner profile is in the clamped position. In one embodiment, the surgical clamp jaw defines one or more flexion assistance voids, wherein at least one of the one or more flexion assistance voids is in contact with a gap between one of the one or more sets of corresponding abutment surfaces.

Abstract: A duplex system measuring and outputting at least one of a voltage and current is provided. A first measurement device measures at least one of the voltage and current. A second measurement device measures at least one of the voltage and current. A control device is disconnected from the first measurement device and performs a changeover to the second measurement device when the first measurement device abnormally operates. A filter filters a second measurement value of the second measurement device based on a first measurement value of the first measurement device to output a filtered value.

Abstract: The present disclosure includes: a first channel unit configured to transmit and receive a data piece with a network bus, to convert the received data piece to an MII data piece, and to transmit and receive the converted MII data piece; a second channel unit configured to transmit and receive a data piece with the network bus, to convert the received data piece to an MII data piece, and to transmit and receive the converted MII data piece; a CPU configured to recognize a carrier detection signal (CRC) of the MII data received from the first channel unit and the second channel unit, and to transmit and receive the MII data; and a monitoring unit configured to perform a data communication with the CPU, and to monitor a data piece by each channel from the MII data received from the CPU.

Abstract: Level shifters are disclosed for high performance sub-micron IC designs. One embodiment is a level shifting device that comprises a first input circuit that toggles a first internal signal between a logical zero of a first voltage range and a logical one of a second voltage range based on an input data signal and an output data signal, and a second input circuit that toggles a second internal signal between a logical zero of the second voltage range and a logical one of the first voltage range based on the input data signal and the output data signal. An output circuit of the device toggles the output data signal between a logical zero of the second voltage range and a logical one of the second voltage range based on the first internal signal, the second internal signal, and a compliment of the input data signal.

Abstract: Methods and systems for generating data transformations to improve ROM yield and programming time. A bit flip register can be configured in association with the ROM and a binary string can be read into the bit flip register on reset. Subsequently, data output from the ROM can be selectively complemented utilizing a content of the bit flip register and the content of the bit flip register can be programmed into the ROM in order to reduce programming time for each ROM. A defective cell can be tolerated by selectively flipping a column with respect to the defective cell to improve yield. A built-in self-test (BIST) engine that generates addresses up to and including content of an address limiting register can be employed to limit the ROM access to a programmed part during testing in order to tolerate defects in any unused location.

Abstract: Disclosed is a system for controlling a water turbine generator for waterworks, which monitors and controls a plurality of water turbine generators, provided in a water pipe, for waterworks in real time to integratedly operate the water turbine generators, contributes to stably generate and secure power, and increases an efficiency of the water turbine generators through integrated management.

Abstract: Systems, methods, devices and circuits for data amplification, and more particularly systems and methods for characterizing distortion introduced during data amplification. In some cases, an amplifier modeling circuit is discussed that receives a preamplifier status input from a preamplifier circuit; applies a vector fitting algorithm to the preamplifier status to yield a pole value; determines that the pole value is greater than unity; and replaces the pole value with an inverse of the pole value when the pole value is greater than unity.

Abstract: An apparatus for detecting speed of a motor is disclosed, the apparatus including an amplifier configured to amplify a two-phase sine-wave signal inputted from an encoder based on rotation of a motor; a first conversion unit configured to convert the two-phase sine-wave signal to a digital data; a second conversion unit configured to convert the two-phase sine-wave signal to a square-wave signal; a counter unit configured to accumulate by counting the square-wave signal; and a speed determination unit configured to determine a speed of the motor, by receiving the digital data from the first conversion unit and the accumulated count from the counter unit.

Abstract: Provided is a molded case circuit breaker eliminating the necessity to install a communication unit and a particular communication medium and allowing for checking an fault type from a front indication operation panel of an enclosure of a power distributing board or from a remote area by simply connecting two signal lines for transmitting a relay switching signal as an accident current indication signal, the circuit breaker comprises a relay assembly including a plurality of fault indicating relays installed in the circuit breaker and configured to generate a fault current indication signal by opening or closing a contact when the indication command signal of a fault current is received from the electronic trip unit, and a signal output terminal configured to output a fault type indication signal of the fault indicating relays to the outside of the circuit breaker.

Abstract: An apparatus includes a hit bitline driver circuit and an equalization control circuit. The hit bitline driver circuit may be configured to drive a pair of hit bitlines responsive to a search bit. The equalization control circuit may be configured to transfer charge from one hit bitline of the pair to the other hit bitline of the pair in response to the search bit changing state.

Abstract: A control device for a voltage source converter connected to a wind farm is provided. The control device includes: a power source monitor unit sensing a direct current (DC) voltage of a whole grid connected to the voltage source converter; and a control unit comparing the DC voltage of the whole grid sensed with a reference voltage, wherein the control unit adjusts an alternating current (AC) supplying to the wind farm to a setting when as a result of comparison, the DC voltage of the whole grid sensed is out of a preset range of reference voltages.

Abstract: Provided is a method for preventing overheating of a traction motor in an electric vehicle. The method for preventing the overheating of the traction motor in the electric vehicle includes identifying magnitude of an output load of the motor, identifying a loading time of the motor on the basis of the identified magnitude of the output load, comparing the identified loading time to a preset critical time, and controlling output torque of the motor according to the comparison result.