Abstract: Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.
Type:
Application
Filed:
March 21, 2014
Publication date:
August 20, 2015
Applicant:
LSI Corporation
Inventors:
Volodymyr Shvydun, Adam B. Healey, Chaitanya Palusa, Hiep T. Pham
Abstract: A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.
Type:
Application
Filed:
March 18, 2014
Publication date:
August 20, 2015
Applicant:
LSI Corporation
Inventors:
Sundararajan Sankaranarayanan, AbdelHakim S. Alhussien, Erich F. Haratsch, Earl Cohen
Abstract: Disclosed are an apparatus and a method for managing alarms based on state information received from systems. The method includes receiving alarms including state information of a remote control system; displaying an alarm queue including at least one of the received alarms; setting important alarms from among the alarms displayed in the alarm queue; and deleting the important alarm from the alarm queue when a user confirms the important alarm or a signal notifying a recovery to a normal state of a system corresponding to the important alarm is received.
Abstract: A method of outputting a positioning pulse by a programmable logic controller (PLC) is provided. The method includes setting up the desired cycle of a pulse to be output; determining a number of needed clocks based on a number of system clocks and a desired frequency according to the desired cycle; determining a total number of needed clocks based on the number of needed clocks and the desired frequency; determining a clock difference based on the number of system clocks and the total number of needed clocks; determining a first number of setup clocks corresponding to a first output pulse in a certain cycle; determining a second number of setup clocks corresponding to pulses except for the first output pulse; and outputting a pulse based on the first number of setup clocks and the second number of setup clocks.
Abstract: Disclosed is a method of detecting the disconnection state of a power cable in an inverter system. The method includes detecting a battery voltage, detecting a DC-link voltage, detecting the disconnection state of the power cable based on a difference value between the detected battery voltage and the DC-link voltage, and stopping driving of a motor if the power cable is detected as being disconnected.
Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory.
Type:
Application
Filed:
February 27, 2014
Publication date:
August 13, 2015
Applicant:
LSI Corporation
Inventors:
Zhengang Chen, Yu Cai, Erich F. Haratsch, Zhimin Dong
Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to (i) classify data from multiple blocks of the memory as hot-read data or non hot-read data, (ii) aggregate the hot-read data to dedicated blocks, and (iii) select a type of error correcting code to protect the hot-read data in the dedicated blocks. The aggregation reduces an impact on endurance of the memory.
Abstract: An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.
Type:
Application
Filed:
February 28, 2014
Publication date:
August 13, 2015
Applicant:
LSI Corporation
Inventors:
AbdelHakim S. Alhussien, Ivana Djurdjevic, Yu Cai, Erich F. Haratsch, Yue Li, Earl T. Cohen
Abstract: A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process.
Type:
Application
Filed:
March 5, 2014
Publication date:
August 13, 2015
Applicant:
LSI Corporation
Inventors:
Xuebin Wu, Yang Han, Weijun Tan, Shaohua Yang
Abstract: Methods are systems for calculating log-likelihood ratios for a decoder utilized in an electronic non-volatile computer storage apparatus are disclosed. A log-likelihood ratio handler is configured to provide an input log-likelihood ratio to the decoder, wherein the input log-likelihood ratio is one of: a uniform input log-likelihood ratio for all bits calculated based on an estimated raw bit error rate for a particular data unit, or a bit-based input log-likelihood ratio for each bit calculated based on a confidence value for a cell containing said each bit. The decoder of the electronic non-volatile computer storage apparatus is configured to decode encoded data at least partially based on the input log-likelihood ratio from the log-likelihood ratio handler.
Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for data synchronization and detection.
Type:
Application
Filed:
February 11, 2014
Publication date:
August 13, 2015
Applicant:
LSI Corporation
Inventors:
Yuqing Yang, Shaohua Yang, Lei Wang, Gu Zhao
Abstract: A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation.
Type:
Application
Filed:
March 5, 2014
Publication date:
August 13, 2015
Applicant:
LSI Corporation
Inventors:
Xuebin Wu, Shaohua Yang, Zhi Bin Li, Haitao Xia
Abstract: The present invention provides an apparatus for charging a high voltage battery of an electric vehicle by performing a control operation when the apparatus operates abnormally, the control operation discontinuing operations of a rectifier, a boost PFC (Power Factor Control) circuit and a DC-DC converter and receiving a power source from an auxiliary power supply unit, the power source charged by discharging a DC-link capacitor.
Abstract: A DC link capacitor assembly is provided. The DC link capacitor assembly according to the embodiment includes a DC link capacitor disposed in a housing. The housing includes a top surface, a bottom surface disposed spaced downward from the top surface, at least one side surface connecting the top surface to the bottom surface, an opening defined at a front side between the top surface and the bottom surface and an external capacitor accommodation part disposed outside the side surface.
Type:
Grant
Filed:
November 7, 2013
Date of Patent:
August 11, 2015
Assignee:
LSIS Co., Ltd.
Inventors:
Han Uk Jeong, Ung Hoe Kim, Hyoung Taek Kim
Abstract: An outage schedule management apparatus and a method are provided, wherein a topology change is executed in response to an outage schedule set up by a user input, and a validity determination is executed to system operation standard to approve an outage.
Abstract: Provided is a method of measuring the presence and/or the amount of glucagon-like peptide-1 (GLP-1) in a sample, which method is characterized by comprising the step of treating the sample in advance with an acidic solution, and a kit of measuring the presence and/or an amount of GLP-1 in a sample, the kit containing (a) the acidic solution, (b) an antibody specific to GLP-1, and (c) an instruction manual.
Abstract: Provided are a train speed measuring device and method. The train speed measuring device includes: at least one first tachometer disposed at an axle of a trailer car and for outputting a pulse signal according to a wheel revolution of the trailer car; at least one second tachometer disposed at an axle of a motor car and for outputting a pulse signal according to a wheel revolution of the motor car; at least one speed measuring unit for measuring speed values on the basis of pulse signals outputted from the at least one first tachometer and the at least one second tachometer; and a speed calculating unit for calculating the speed of the train on the basis of the measured speed values.
Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory.
Abstract: Applications that use non-volatile random access memory (NVRAM), such as those that apply file system journal writes and database log writes where write operations apply data sequentially over the NVRAM, map the available capacity of the NVRAM in a virtual address space without compromising performance. The NVRAM is segmented into regions with multiple such regions fitting within a volatile RAM element accessible to the application and the NVRAM. One or more regions are loaded in the volatile RAM and reflected in page tables that reference the regions. The page tables are managed on a host computer executing the application. One region space in the volatile RAM is unused and available for transferred information. Mechanisms are provided for dynamically transferring regions and interfacing with the host computer. As the application sequentially accesses information in the stored regions, older regions are removed and new regions loaded from NVRAM to the volatile RAM.
Type:
Application
Filed:
February 27, 2014
Publication date:
August 6, 2015
Applicant:
LSI Corporation
Inventors:
Saugata Das Purkayastha, Luca Bert, Philip K. Wong, Anant Baderdinni
Abstract: A method of operating a multi-reader two-dimensional magnetic recording system includes determining a position of a multi-reader head of the multi-reader two-dimensional magnetic recording system, determining an areal density push according to the position of the multi-reader head, and performing an operation to read data from or write data to a magnetic recording medium according to the areal density push.