Abstract: Provided is a capacitor structure for a three-dimensional AND flash memory device. The capacitor includes a substrate having a capacitor array region and a capacitor staircase region, a circuit under array (CuA) structure disposed on the substrate, a bottom conductive layer disposed on the CuA structure, a stacked structure disposed on the bottom conductive layer, and pillar structures. The stacked structure includes dielectric layers and conductive layers alternately stacked. The conductive layers in the capacitor staircase region are arranged in a staircase form. The pillar structures are arranged in an array in the capacitor array region and penetrate through the stacked structure and the bottom conductive layer. A part of the conductive layers is 10 electrically connected to a first common voltage source, and the rest of the conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

Abstract: Disclosed herein is related to physical unclonable function (PUF) with enhanced security based on one time programmable (OTP) memory device. In one aspect, indirection process, hashing or a combination of them can be employed to hide a key for allowing access to an integrated circuit. Each indirection process may include identifying a subsequent address of the OTP memory device based on content stored by the OTP memory device at an address, and obtaining subsequent content stored by the OTP memory device at the subsequent address. Through a number of indirection processes, hidden content stored by the OTP memory device can be obtained. In one approach, hashing can be applied to input bits to obtain an address of the OTP memory device to apply. In one approach, hashing can be applied to the hidden content stored by the OTP memory device to generate the key.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type that has a main surface and that includes a device region, a base region of a second conductivity type that is formed in a surface layer portion of the main surface at the device region, a source region of the first conductivity type that is formed in a surface layer portion of the base region at an interval inward from a peripheral portion of the base region and that defines a channel region with the semiconductor layer, a base contact region of the second conductivity type that is formed in a region different from the source region at the surface layer portion of the base region and that has an impurity concentration exceeding an impurity concentration of the base region, a well region of the first conductivity type that is formed in the surface layer portion of the main surface at an interval from the base region at the device region and that defines a drift region with the base region, a drain region of the first conductivi

Abstract: The present disclosure provides a plug connector, including: a mounting plate including a first side having an electrical component area; a first electrical component cavity and a second electrical component cavity arranged in the electrical component area; a first electrical component arranged in the first electrical component cavity and a second electrical component arranged in the second electrical component cavity. The plug connector further includes a groove, a sealing ring arranged in the groove and a fixing plate arranged on the first side, wherein the sealing ring is arranged between the fixing plate and the mounting plate. The plug connector can provides a waterproof function during a floating insertion of a mating connector.

Abstract: In some embodiments, the techniques described herein relate to a multilayered semiconductor diode device including: a substrate including silicon carbide (SiC); an epitaxial drift layer including a first semiconductor oxide material or SiC on the substrate; an epitaxial channel layer including a second semiconductor oxide material on the epitaxial drift layer; and a metal layer above the epitaxial drift layer to form a Schottky barrier junction. The epitaxial channel layer and the Schottky metal layer form a mesa structure contacting a sidewall layer. In some embodiments, a method of forming a multilayered semiconductor diode device includes: providing a substrate including silicon carbide (SiC); forming an epitaxial drift layer; forming an epitaxial channel layer; forming a metal layer to form a Schottky barrier junction; etching the epitaxial channel layer and the metal layer to form a mesa structure; and forming a sidewall layer contacting a wall of the mesa structure.

Abstract: A semiconductor light emitting device comprises a current confinement layer and a semiconductor light emitting stack. The semiconductor light emitting stack is disposed on the current confinement layer and has a bottom surface in contact with the current confinement layer. The current confinement layer includes an insulating layer and a plurality of conductive portions. The plurality of conductive portions are disposed in the insulating layer in contact with the bottom surface. An area ratio of the plurality of conductive portions to the bottom surface is 7% or more and 15% or less.

Abstract: A semiconductor device includes an active region, a first-conductivity-type region, and a termination region. The active region has first second-conductivity-type regions, silicide films, and a first electrode; the termination region has a second second-conductivity-type region. The active region is configured by ohmic regions where the first electrode is in contact with the silicide films, and Schottky regions where the first electrode is in contact with the first-conductivity-type region. When a doping concentration of the first-conductivity-type region is a low concentration, a greater number of the ohmic regions is provided in a chip center portion than in a chip outer peripheral portion and when the doping concentration of the first-conductivity-type region is a high concentration, a greater number of the ohmic regions is provided in the chip outer peripheral portion than in the chip center portion.

Abstract: Provided by the present disclosure is a power distribution box having a data interaction function, comprising a moving mechanism, a control mechanism and a data interaction mechanism. The moving mechanism comprises an electric valve and an electric telescopic rod. The control mechanism comprises a main control single-chip microcomputer and a control panel. The data interaction mechanism comprises a power distribution box tester and an output port. The electric valve is electrically connected to the main control single-chip microcomputer and is arranged at the bottom of the power distribution box. The control panel is arranged on a support rod and is electrically connected to the main control single-chip microcomputer. The power distribution box tester is electrically connected to the main control single-chip microcomputer and is arranged in the power distribution box, and the power distribution box tester is used for testing electrical devices of the power distribution box.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type; a gate electrode positioned on the semiconductor substrate; and a semiconductor part embedded in the semiconductor substrate and having the first conductivity type, in which the semiconductor substrate is provided with at least a part of a drift region being adjacent to the semiconductor part and having a second conductivity type, and a surface of the semiconductor part and a first portion included in a surface of the drift region are positioned higher than a second portion in a surface of the semiconductor substrate, the second portion being positioned below the gate electrode.

Abstract: An inverter includes a first power board, a second power board, and a first filter circuit, a second filter circuit, and a third filter circuit. The first power board is configured to fasten an inverter circuit and the first filter circuit. The second filter circuit includes one or more inverter inductors, and an output end of the inverter inductor is electrically connected to an input end of the first filter circuit through a first wire and the first power board sequentially. The second power board is configured to fasten the third filter circuit, the third filter circuit is electrically connected to the output end of the inverter inductor through the second power board and a second wire sequentially, and the third filter circuit is further configured to electrically connect to a power grid or a load.

Abstract: A semiconductor device comprises an epitaxial layer, a first trench, a first field plate, a first trench gate, a first planar gate, and a first conductive connection portion. The first trench is disposed in the epitaxial layer and extends along a first direction. The first field plate is disposed in the first trench and extends along the first direction. The first trench gate is disposed in the first trench and extends along the first direction, where the first trench gate is laterally separated from the first field plate. The first planar gate is disposed on the first field plate and the first trench gate. The first conductive connection portion is disposed in the first trench and located between the first trench gate and the first planar gate, and the first trench gate is electrically connected to the first planar gate through the first conductive connection portion.

Abstract: Disclosed is a cell balancing device. The cell balancing device includes a balancing switching unit in which source stages of a first switch and a second switch are connected in series in common and drain stages of the first switch and the second switch are connected in parallel to both ends of a battery cell, respectively, a latch unit interposed between the source stage of the balancing switching unit and a sensing pin of the battery cell and configured to drive a balancing switching unit by outputting a driving voltage to a gate stage of the balancing switching unit by receiving an enable signal and an inversion enable signal, and a reverse voltage protection unit interposed between the source stage of the balancing switching unit and the sensing pin of the battery cell.

Abstract: A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.

Abstract: A high voltage direct-mounted energy storage method and system for eliminating a frequency multiplying current in battery charge and discharge is provided.

Abstract: A semiconductor device includes a channel portion disposed on and spaced apart from a substrate, a gate dielectric which includes an upper dielectric region disposed on the channel portion, a first inner gate structure disposed between the substrate and the upper dielectric region, and an outer gate structure including an outer work-function portion and a cap portion. The outer work-function portion covers the upper dielectric region and the first inner gate structure. The cap portion covers the outer work-function portion in a way that the cap portion is separated from the first inner gate structure. The first inner gate structure includes a first work-function material and a conductive material that is different from the first work-function material. The outer work-function portion includes a second work-function material that is different from the conductive material.

Abstract: Provided is a power management device including a first power domain operating in a sleep mode consuming minimal power, and a second power domain turned on exclusively when a wake signal is received from an external device within a communication range of the first power domain, wherein the first power domain includes an always-on Digital Low-DropOut (DLDO), and the second power domain includes a main Low-DropOut (LDO), and split sequence control is performed on power management in the first power domain and the second power domain.

Abstract: A PWM signal conversion circuit and method, and an LED dimming system. The circuit includes: a PWM signal detection module, which outputs a first voltage corresponding to a low-level time of the PWM signal and a second voltage corresponding to a high-level time of the PWM signal; an addition module, which sums the first and second voltages to obtain a third voltage; a switch signal generation module, which generates a switch signal based on the third voltage; a duty cycle ratio generation module, which obtains a duty cycle ratio of the PWM signal based on a counting to the high level of the PWM signal by the switch signal; and an output voltage generation module, which obtains an output voltage related to a duty cycle of the PWM signal based on the duty cycle ratio.

Abstract: This application provides a paging method and an apparatus. In the paging method, a first core network device sends first signaling to a first device, indicating to the first device to page a terminal device. The first device may send second signaling, where the second signaling may indicate information about a first flag. The information about the first flag indicates that a type of a flag of a to-be-paged terminal device is a first type and/or a state of the flag is a first state, to determine the to-be-paged terminal device. In this way, a mechanism for paging the terminal device is provided, and there is no need to determine which terminal device is to be paged. This helps simplify the process of paging the terminal device.

Abstract: The application discloses a POL integrated power supply module and a production process thereof. The POL integrated power supply module comprises an inductor assembly, a substrate, a switch unit and an input capacitor. The substrate comprises a first surface and a second surface which are opposite, the inductor assembly is arranged on the second surface of the substrate, and the switch unit and the input capacitor are arranged on the first surface of the substrate. According to the POL integrated power supply module, a structural layout is provided, and the ultrathin thickness of the POL integrated power supply module is achieved. According to the POL integrated power supply module with the structure, a corresponding production process is provided, the production process is simplified, and the reliability of the POL integrated power supply module is improved.

Abstract: The present disclosure discloses a sensing function control node for an Internet of Things (IoT), and relates to technical field of electrical communication. The node includes an accessing module for sensors and actuators, a data format analyzing and integrating module and a transmission accessing and connecting module. Software-defined optical access technologies are utilized to control original sensing data in the IoT to access the accessing module for the sensors and the actuators. Status information of modules in the node is sensed in real time through a software-defined unified control plane, to adjust upload rates of modules and control the connections between sensing function control node and EAN. The original sensing data in IoT are transmitted to the transmission accessing and connecting module after being pre-processed. The pre-processed data are transmitted to EAN through upload channels between the sensing function control node and EAN established.