Abstract: A multilayer electronic component includes a body including first and second surfaces facing each other in a first direction, and third and fourth surfaces connected to the first and second surfaces and facing each other in a second direction, and including a capacitance forming portion including a dielectric layer and first and second internal electrodes alternately disposed with the dielectric layer interposed therebetween, a lower cover portion disposed between the first surface and the capacitance forming portion, and an upper cover portion disposed between the second surface and the capacitance forming portion, a first external electrode disposed on the third surface, and a second external electrode disposed on the fourth surface, wherein, among the upper cover portion and the lower cover portion, only the upper cover portion includes a buffer electrode.

Abstract: A capacitor module that includes: a plurality of capacitors each including: a first electrode and a second electrode that face each other, and a side surface joining the first electrode and the second electrode, the side surface having a pair of flat portions that face each other, and a pair of curved portions joining the pair of flat portions to each other, the plurality of capacitors being arrayed in a row such that the flat portions of adjacent capacitors face each other; at least one metal sheet arranged in any of spaces between the flat portions of the adjacent capacitors, the at least one metal sheet being in contact with the first electrode of at least one of the adjacent capacitors; a first bus-bar electrically connected to the at least one metal sheet; and a second bus-bar electrically connected to each of the second electrodes of the plurality of capacitors.

Abstract: Disclosed are an electronic stylus and an electronic device. The electronic stylus includes: a pen casing and a stress transmitting structure provided in the pen casing; the stress transmitting structure includes a strain piece and a pen core bracket connected to the pen core; the strain piece includes a fixed section, a stress section and a detecting section, and the stress section and the detecting section are respectively connected to two ends of the fixed section and are bent and extended; the pen core bracket is configured to run through the stress section and is connected to the stress section and the detecting section, and the detecting section is provided with a strain gauge; and the fixed section is configured to extend toward a stress direction of the pen core, and the fixed section is welded to an inner wall of the pen casing.

Abstract: A roller input device includes a base, a roller, a magnetic assembly, and a magnetic-conductive element. The roller is rotatably disposed on the base and includes a main body and magnetic protrusions arranged around a peripheral portion of the main body. The magnetic assembly is disposed on one side of the base and includes an electromagnet and a permanent magnet. The electromagnet includes a coil. The magnetic-conductive element is disposed on the base and between the roller and the magnetic assembly, and a side surface of the magnetic-conductive element facing the roller has a convex portion. When the electromagnet is in a first mode, the coil conducts a forward current, so that the magnetic-conductive element is magnetized to have a magnetic property. When the electromagnet is in a second mode, the coil conducts a reverse current, so that the magnetic-conductive element does not have the magnetic property.

Abstract: A display device includes: a pixel including a light emitting element; a sensor including a sensing element and a sensor driving circuit; and a sensor driver to output a sensor scan signal to the sensor driving circuit. The sensor driver includes: a switching circuit connected between a first input terminal for receiving a first clock signal of a first operating frequency and a first clock node, and to output a first filtering clock signal of a second operating frequency to the first clock node in response to a first enable signal; and a driving circuit to output the sensor scan signal in response to the first filtering clock signal of the first clock node.

Abstract: A proximity detection device with a detection distance for detecting an object separated to some extent from an operation surface is provided. The proximity detection device includes a proximity detection unit that has a piezoelectric body and first and second electrodes disposed in contact with the piezoelectric body to detect proximity of an object, a signal applying unit that causes the proximity detection unit to perform capacitance detection and ultrasonic transmission and/or ultrasonic reception by applying a plurality of signals of different frequencies to at least one of the first and second electrodes, and a charge measurement unit connected to at least one of the first and second electrodes to measure electric charge.

Abstract: An input sensor and display device including the same are capable of sensing a touch (or touch interaction) by a user's body and a touch by an electronic pen.

Abstract: Systems and methods for performing bulk actions on multiple graphical objects are described herein. The presently disclosed systems and methods may provide a client interface which may allow a user to select multiple objects and a bulk action interface which may allow a user to select one or more bulk actions that may be applied to issues associated with the previously selected multiple objects. In response to a selection of the one or more bulk actions, the systems and methods disclosed may cause the selected one or more bulk actions to be performed with respect to each of the selected multiple objects.

Abstract: An object is to provide an information terminal device that improves convenience of use in operation mode control of an application that performs cooperative operation with a plurality of information terminal devices, and an application operation mode control method of same. Accordingly, an information terminal device that executes applications is configured to activate an application by selecting between a solo operation mode and a cooperative operation mode, depending on a form of activation instruction for the application.

Abstract: A data stream architecture-based accelerator includes a storage unit, a read-write address generation unit and a computing unit. The storage unit includes a plurality of banks. The read-write address generation unit is used for generating storage unit read-write addresses according to a preset read-write parallelism, determining target banks in the storage unit according to the storage unit read-write addresses and reading to-be-processed data from the target banks for operations in the computing unit. The computing unit includes a plurality of data paths and is configured to determine target data paths according to a preset computing parallelism so that the target data paths can perform operations on the to-be-processed data to obtain processed data, and then store the processed data into the target banks according to the storage unit read-write addresses.

Abstract: A method for non-blocking multithreading, the method may include (a) providing, during a deep neural network (DNN) calculation iteration, to a shared computational resource, input information units related to multiple DNN threads; (b) determining whether to reduce a numerical precision of one or more DNN calculations related to at least one of the multiple DNN threads, and (c) executing, based on the determining, DNN calculations on at least some of the input information units to provide one or more results of the DNN processing.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, an isolation layer, a first electronic device, a first interconnection structure, a first conductive structure, and a second conductive structure. The substrate has a first surface and a second surface opposite the first surface. The isolation layer contacts the second surface of the substrate and has a first surface facing away from the substrate. The first electronic device is embedded in the substrate. The first interconnection structure extends from the first surface of the substrate to the first surface of the isolation layer. The first conductive structure is disposed on the first surface of the substrate. The second conductive structure contacts the first surface of the isolation layer. The first conductive structure and the second conductive structure are electrically connected by the first interconnection structure.

Abstract: Improved control of via anchor profiles in metals at a contact layer can be achieved by slowing down an anchor etching process and by introducing a passivation operation. By first passivating a metallic surface, etchants can be prevented from dispersing along grain boundaries, thereby distorting the shape of the via anchor. An iterative scheme that involves multiple cycles of alternating passivation and etching operations can control the formation of optimal via anchor profiles. When a desirable anchor shape is achieved, the anchor maintains structural integrity of the vias, thereby improving reliability of the interconnect structure.

Abstract: A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.

Abstract: A semiconductor package includes a redistribution substrate including a conductive structure having a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern, on the lower conductive pattern, an insulating structure covering at least a side surface of the redistribution structure, and a protective layer between the lower conductive pattern and the insulating structure, a semiconductor chip on the redistribution substrate, and a lower connection pattern below the redistribution substrate and electrically connected to the lower conductive pattern. The protective layer includes a first portion in contact with at least a portion of an upper surface of the lower conductive pattern, and a second portion in contact with at least a portion of a side surface of the lower conductive pattern.

Abstract: Bonding system for bonding a second article to a first article, comprising an activation treatment device that comprises an object supporter that supports objects comprising the second article, and a particle beam source that activates a bonding surface of the second article by irradiating the objects with a particle beam, the objects being set on one treatment surface without being opposed to each other, followed by performing activation treatment by the particle beam source; and a bond device that brings the second article, of which the bonding surface is activated by the activation treatment device, into contact with the first article, to thereby bond the second article to the first article, wherein the object supporter supports the objects in a posture in which a portion formed of a plurality of kinds of materials comprising the bonding surface of the second article in the objects is exposed to the particle beam source.

Abstract: A chip package structure includes a first chip, a second chip, and a carrier board. The first chip is disposed between the second chip and the carrier board. An active layer of the first chip is opposite to an active layer of the second chip. A first interconnection structure is disposed between the first chip and the second chip and is configured to couple the active layer of the first chip to the active layer of the second chip. A first conductor pillar is disposed in the first chip. One end of the first conductor pillar is coupled to the active layer of the first chip, and the other end of the first conductor passes through the first chip to be coupled to a circuit in the carrier board.

Abstract: A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.

Abstract: In one example, a semiconductor structure comprises a frontside substrate comprising a conductive structure, a backside substrate comprising a base substrate and a cavity substrate contacting the base substrate, wherein the backside substrate is over a top side of the frontside substrate and has a cavity and an internal interconnect contacting the frontside substrate, and a first electronic component over the top side of the frontside substrate and in the cavity. The first electronic component is coupled with the conductive structure, and an encapsulant is in the cavity and on the top side of the frontside substrate, contacting a lateral side of the first electronic component, a lateral side of the cavity, and a lateral side of the internal interconnect. Other examples and related methods are also disclosed herein.

Abstract: An electronic package is provided and includes at least one electronic element, at least one first conductive structure and a second conductive structure disposed on one side of a carrier structure with at least one circuit layer, and an encapsulation layer covering the electronic element, the first conductive structure and the second conductive structure, where the first conductive structure is exposed from the encapsulation layer to externally connect required elements according to functional requirements.