Abstract: A laser source includes a laser source housing, laser arrays and a beam path assembly. The laser source housing includes beam outlet and accommodating openings disposed at a same side wall or different side walls of the laser source housing. The laser arrays are respectively disposed in the accommodating openings. A laser array is configured to emit laser beams into the laser source housing. A laser-exit surface of the laser array includes a plurality of laser-exit regions configured to emit laser beams of multiple colors. The beam path assembly including a plurality of combining lens groups is disposed inside the laser source housing. The combining lens groups and the laser arrays are in one-to-one correspondence. A combining lens group is configured to combine laser beams of multiple colors emitted by a corresponding laser array, and combined laser beams are not located in beam output paths of other combining lens groups.

Abstract: A timepiece including a microgenerator (100), formed by a stator (20) including permanent magnets (25) and a rotor (10) including coils (11) and at least one light-emitting diode (31, 32), which is powered, either directly or indirectly via an electrical and/or electronic circuit, by at least one of the coils which supplies an electric current induced when it rotates relative to the stator (20). The rotor carries all of the electrical and electronic equipment formed by the at least one light-emitting diode, the coils and, where appropriate, the electrical and/or electronic circuit.

Abstract: A composition for an encapsulant film, comprising an ethylene/alpha-olefin copolymer, an organic peroxide crosslinking agent, a crosslinking auxiliary agent and a silane coupling agent. If an encapsulant film is manufactured using the composition for an encapsulant film, the immersion time of an ethylene/alpha-olefin copolymer may be reduced, and the economic feasibility of the production process of the encapsulant film may be improved. In addition, the composition for an encapsulant film shows an excellent degree of crosslinking. The encapsulant film comprising the composition for an encapsulant film and a solar cell module comprising the encapsulant film are also provided.

Abstract: Disclosed are a display panel and a display device. The display panel includes an active area and a non-active area arranged in a first direction; where the active area includes a plurality of first signal lines extending in the first direction and arranged in a second direction, the first direction intersecting the second direction; the non-active area also includes a plurality of fan-out lines electrically connected to the plurality of first signal lines, respectively; a bending area is provided with a plurality of avoidance areas, and the fan-out lines avoid the avoidance areas; in two fan-out lines adjacent to the avoidance area in the second direction and on different sides of the avoidance area, a section of one fan-out line in a first fan-out area includes a first extension segment and a second extension segment connected to the first extension segment.

Abstract: A semiconductor device includes a substrate. A gate structure is over the substrate. Source/drain epitaxial structures are on opposite sides of the gate structure. An interlayer dielectric (ILD) structure surrounds and covers the gate structure. A dielectric liner lines a sidewall of the ILD structure and wraps a top corner of the gate structure. The dielectric liner comprises a bottom portion, a top portion above the bottom portion, and a middle portion connecting the bottom portion and the top portion, wherein the middle portion has a different composition than the bottom portion and the top portion.

Abstract: The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.

Abstract: A semiconductor package includes a base semiconductor chip, a first chip structure including first semiconductor chips that are vertically stacked on the base semiconductor chip, and a second chip structure disposed on the first chip structure and including second semiconductor chips that are vertically stacked on the first chip structure. Inactive surfaces of the first semiconductor chips are oriented in a first direction with respect to the base semiconductor chip, and active surfaces of the second semiconductor chips are oriented in the first direction with respect to the base semiconductor chip.

Abstract: A semiconductor package is provided and includes: a glass substrate including a cavity; a logic chip within the cavity; a memory device on the glass substrate and the logic chip; a first redistribution structure between the memory device and the glass substrate and connected to the memory device and the glass substrate; a second redistribution structure below the glass substrate and connected to the glass substrate and the logic chip; and a package encapsulation layer that surrounds the memory device and the logic chip on the second redistribution structure.

Abstract: A semiconductor package includes a package substrate including a first conductive pad at an upper portion thereof, a lower semiconductor chip stack structure including dynamic random access memory chips that are stacked in a vertical direction on the package substrate and electrically connected to each other by a through electrode, an upper semiconductor chip stack structure including flash memory chips, each of the flash memory chips may include a second conductive pad at an upper portion thereof, stacked in the vertical direction on the lower semiconductor chip stack structure, a conductive connection pattern contacting an upper surface of the first conductive pad and extending in the vertical direction, and a bonding wire contacting at least one of the second conductive pads and being electrically connected to the conductive connection pattern.

Abstract: A navigation planning system and method can comprise: acquiring a planned route indicating a navigation planning route of a movable body on a water; acquiring movable body information including a position, a moving direction, and a speed of the movable body; acquiring obstacle information including a position, a moving direction, and a speed of one or a plurality of obstacles around the movable body; and calculating a collision risk value indicating a risk level of collision between the movable body and an obstacle from the plurality of obstacles based on the movable body information and the obstacle information, and determining necessity of evasion based on the collision risk value and a threshold value. In the case of necessity of evasion, the system can set an evasion route whose end point is not on the planned route and whose direction at the end point is in a predetermined direction.

Abstract: The display device includes a display panel including a plurality of pixels; a driver IC configured to convert digital data corresponding to an input image to an analog voltage using a gamma voltage, and to supply the analog voltage to the plurality of pixels; and a power supply configured to supply a pixel driving voltage to the display panel and the driver IC. The driver IC includes a weight selector configured to select a weight for adjusting the gamma voltage based on a change amount of the pixel driving voltage supplied from the power supply; and a gamma reference voltage generating unit configured to generate a gamma reference voltage based on the selected weight.

Abstract: Provided is a battery system, including a first battery pack including a first battery cell, a second battery pack including a second battery cell, a charger, and at least one processor configured to control the charger to sequentially perform constant current (CC) charging on the second battery pack and the first battery pack based on input power being identified, and control the charger to sequentially perform constant voltage (CV) charging on the second battery pack and the first battery pack based on the CC charging of the second battery pack and the first battery pack being completed, wherein a discharging performance of the first battery pack is greater than a discharging performance of the second battery pack, and wherein a charging performance of the second battery pack is greater than a charging performance of the first battery pack.

Abstract: A charge field-effect linear charger for charging a battery may include a charge pump configured to drive a field-effect transistor external to the charge field-effect linear charger and a variable output impedance for the charge pump, the variable output impedance depending on a mode of operation of the charge field-effect linear charger and an impedance of the field-effect transistor.

Abstract: Embodiments of this application provide a communication method and a related apparatus, so that a first communication apparatus reports first performance indicator information to a second communication apparatus, thereby helping the second communication apparatus determine a nonlinear compensation status of first coefficient information for a power amplifier. This helps the second communication apparatus determine appropriate transmit power for the power amplifier, and improves linearity of a signal output by the second communication apparatus, thereby improving performance of the second communication apparatus. The method in embodiments of this application includes: A first communication apparatus receives a first signal from a second communication apparatus, where the first signal is a signal obtained by performing nonlinear compensation based on first coefficient information.

Abstract: Provided are channel state information processing methods and apparatuses. The method includes: determining a target compression algorithm; compressing Channel State Information (CSI) using the target compression algorithm to obtain compressed CSI; and sending the compressed CSI to a network device.

Abstract: A wire includes: a core; and a shell that covers an outer periphery of the core, wherein the core includes silver, the shell includes 33.0 mass % or more and 37.0 mass % or less of nickel, 9.0 mass % or more and 10.5 mass % or less of molybdenum, 19.0 mass % or more and 21.0 mass % or less of chromium, 0.5 mass % or more and 1.2 mass % or less of titanium, and a remainder including cobalt and an inevitable impurity, a diameter of the wire is 100 ?m or less, and an elongation of the wire is 12% or more.

Abstract: Provided is a battery module assembly in which unit modules are stacked. Each of the unit modules includes: a plurality of battery cells; and a plurality of cartridge assemblies for respectively fixing the plurality of battery cells. The battery module assembly includes: a sensing assembly mounted to upper ends of the plurality of cartridge assemblies and assembled thereto; a front cover for covering front surfaces of the cartridge assemblies; and a connector coupled and fixed to the front cover. The connector includes: a connector body; and a first protrusion region that protrudes from the connector body. An upper sensing assembly connection hole is formed in an upper region of each of the cartridge assemblies.

Abstract: A battery module, and a battery pack and a vehicle including the same are disclosed. A battery module according to an embodiment of the present disclosure includes a plurality of battery cells; a case in which the plurality of battery cells are accommodated; a cover coupled to the case; at least one cooling block coupled to the cover and in contact with the case to cool the battery cell; and a cooling pipe coupled to the cooling block, wherein the cooling block has a variable coupling position in the cover.

Abstract: A battery module according to one embodiment of the present disclosure includes: a plurality of battery cells; a module casing that accommodates the plurality of battery cells, and having a first venting hole on one side surface, the first venting hole that discharges venting gas to outside; and a rupture member coupled to the module casing so as to cover the first venting hole from both sides, and that is at least partially ruptured by the venting gas.

Abstract: Provided are a semiconductor device, and/or an electronic device and a memory device both including the semiconductor device. The semiconductor device includes a lower electrode, an upper electrode spaced apart from the lower electrode, a channel layer between the lower electrode and the upper electrode, a gate insulating layer in the channel layer, an insertion layer provided between the channel layer and the gate insulating layer, and a gate electrode on the gate insulating layer. The channel layer has a vertical channel structure extending in a vertical direction from the lower electrode toward the upper electrode. The insertion layer may include a nitride of a metal and/or an oxynitride of a metal, and the metal may include one or more of niobium (Nb), vanadium (V), or tantalum (Ta).