Abstract: An anti-erosion structure of a motor includes a housing configured to accommodate a stator, a rotor disposed inside the stator, and a shaft disposed inside the rotor; a rear cover coupled to a rear side of the housing; and a ground structure configured to ground the shaft. The ground structure includes a ground bearing installed on the shaft, and a conductor bar having one side fixed to the rear cover and another side contacting the ground bearing.

Abstract: A switching regulator, system-on-chip including the switching regulator, and operating method of the switching regulator are provided. The switching regulator comprises a first inductor having a first end connected to a first node and a second end connected to an output terminal, a second inductor having a first end connected to a second node and a second end connected to the output terminal, a flying capacitor having a first end connected to the first node and a second end connected to the second node, and control circuitry configured to at each of first through fourth times control the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the eighth switch to cause the flying capacitor to store a voltage corresponding to a difference between currents flowing in the first inductor and the second inductor.

Abstract: A bit line sense amplifier includes a differential amplifier configured to receive an input signal from a bit line through an input terminal of the bit line sense amplifier and output a first signal to a first node of the bit line sense amplifier, a sensing inverter configured to receive the first signal and output a second signal to a second node of the bit line sense amplifier, the second signal resulting from inverting the first signal, a first switch configured to electrically connect the second node to a positive input of the differential amplifier, a second switch configured to electrically connect the first node to the positive input of the differential amplifier, and a third switch configured to electrically connect the second node to a negative input of the differential amplifier.

Abstract: A memory device includes a multi-phase clock generator configured to generate first to N-th clock signals having N different phases based on a clock signal from the memory controller, and a monitoring clock signal generator configured to generate a monitoring clock signal having a logic state corresponding to a data pattern in synchronization with edges of the first to N-th clock signals, wherein the monitoring clock signal includes a first monitoring clock signal configured to detect a skew between the first and third clock signals in a first step of a training operation, a second monitoring clock signal configured to detect a skew between the second and fourth clock signals in a second step of the training operation, and a third monitoring clock signal configured to detect a skew between the first and second clock signals in a third step of the training operation.

Abstract: A Static Random Access Memory (SRAM) cell includes a first boundary and a second boundary opposite to, and parallel to, the first boundary, a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate over the channel as a second source/drain region. The SRAM cell further includes a first, a second, a third, and a fourth active region, each extending from the first boundary to the second boundary.

Abstract: Disclosed herein are systems, methods and apparatuses related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

Abstract: An integrated chip including a substrate. A gate layer is over the substrate. A channel layer is over the substrate and vertically spaced apart from the gate layer. A ferroelectric layer is directly between the channel layer and the gate layer. A pair of source/drain electrodes are laterally spaced apart over the channel layer. A plurality of charge traps are along an interface between the ferroelectric layer and the channel layer.

Abstract: A method and apparatus with flash memory control are provided. The method includes performing first programming on a target memory cell of a cell array while adjusting a first programming time and a programming voltage, when a cell current of the target memory cell is determined to satisfy a primary target in association with the first programming, performing second programming on the target memory cell while adjusting a second programming time, and when the cell current of the target memory cell is determined to satisfy a secondary target in association with the second programming, terminating programming on the target memory cell.

Abstract: A method of decoding a coded video bitstream implemented by a video decoder is provided. The method includes the video decoder determining whether a value for a first flag is provided by an external input; setting a first flag equal to the value provided by the external input and a second flag equal to the value of the first flag to prevent a gradual decoding refresh (GDR) picture from being output when the value for the first flag is provided by the external input; decoding the GDR picture; and storing the GDR picture in a decoded picture buffer (DPB).

Abstract: A data generation method is for generating video data that covers a second luminance dynamic range wider than a first luminance dynamic range and has reproduction compatibility with a first device that does not support reproduction of video having the second luminance dynamic range and supports reproduction of video having the first luminance dynamic range, and includes: generating a video signal to be included in the video data using a second OETF; storing, into VUI in the video data, first transfer function information for identifying a first OETF to be referred to by the first device when the first device decodes the video data; and storing, into SEI in the video data, second transfer function information for identifying a second OETF to be referred to by a second device supporting reproduction of video having the second luminance dynamic range when the second device decodes the video data.

Abstract: A lens device is provided that outputs an action state of a lens while utilizing a multi-purpose communication interface capable of connecting a large number of camera devices. The lens device includes: a lens mechanism that is built into a lens main body and forms the optical image; a drive control unit that is built into the lens main body and drive-controls the lens mechanism; a control unit that includes a microcomputer and outputs a drive control signal to the drive control unit; a first connection unit that forms a first communication interface capable of having input/output communication with the control unit, and is capable of connecting to a network; and a second connection unit that includes a second communication interface capable of outputting a signal from the control unit.

Abstract: An electronic device includes a first camera including a first lens and having a first field of view, a second camera including a second lens module and having a second field of view, a first Optical Image Stabilization (OIS) driver; a second OIS driver; and a processor configured to: operate the first camera as a main camera; position a center of the first lens at a first point; position a center of the second lens at a point on a first axis passing the first point; detect an event of switching the main camera to the second camera; based on the event being detected, operate the second camera as the main camera; move the center of the second lens to a second point; and move the center of the first lens to a point on a second axis and passing the second point.

Abstract: An illumination device irradiates a field of view with pulsed illumination light. In a multi-tap type image sensor, one pixel has a plurality of FD (floating diffusion) regions. A camera controller controls a light emission timing of the illumination device and an exposure timing of the image sensor. A pulse exposure region, which is one of the plurality of FD regions, is allocated to generation of a slice image, and a continuous exposure region, which is another one of the plurality of FD regions, is allocated to generation of a normal image. The image sensor generates the slice image by performing multiple exposure of reflected light of the pulsed illumination light from the field of view using the pulse exposure region, and generates the normal image by performing exposure using the continuous exposure region in a section where the pulse exposure region is not used.

Abstract: The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. A method executed by a first node in a wireless communication system is provided. The method may include: establishing a bearer for transmitting a first message; and receiving, from a second node, related information about transmission of the first message. The first message is sent by a user equipment (UE) in an idle mode or an inactive state to the second node via the bearer.

Abstract: An electronic device includes a housing with a mounting hole, a camera module, and a decorative part. The camera module includes a lens and a module body connected to the lens. The decorative part includes a decorative part body and a skirt structure connected to the decorative part body. The skirt structure is provided with a notch. The notch is opposite to the module body. The skirt structure of the decorative part does not interfere with the camera module, such that the camera module is less prone to being damaged by the skirt structure.

Abstract: A display apparatus includes a pixel circuit on a display area of a substrate; a first signal line on the display area transmitting a first signal to the pixel circuit; a first connection line disposed on a first line area, electrically connected to the first signal line, and disposed on a different layer from the first signal line; a first bridge metal that electrically connects the first signal line to the first connection line; a second signal line disposed on the display area and transmitting a second signal to the pixel circuit; a second connection line disposed on the first line area, electrically connected to the second signal line, and disposed on a different layer from the second signal line; and a second bridge metal that connects the second signal line to the second connection line.

Abstract: A battery member includes: a current collector; an electrode mixture layer provided on the current collector; and an electrolyte layer provided on the electrode mixture layer, in which the electrode mixture layer contains an electrode active material, an organic solvent, a polymer, and an electrolyte salt, and the electrolyte layer contains a polymer, an oxide particle, and an electrolyte salt.

Abstract: A temperature raising device includes a switch element control unit that executes a duty ratio control process of increasing one duty ratio which is one of duty ratios of a first switch element and a second switch element and a duty ratio of a third switch element from 0% from an initial state where the first switch element, the second switch element, and the third switch element are in a non-energized state, and decreasing another duty ratio which is another of the duty ratios of the first switch element and the second switch element and the duty ratio of the third switch element from 100% from the initial state by an increased amount of the one duty ratio which is one of the duty ratios of the first switch element and the second switch element and the duty ratio of the third switch element, with respect to an AC generation circuit including a first capacitor, a second capacitor, the first switch element, the second switch element, and the third switch element.

Abstract: Methods and apparatuses for accurately estimating an internal temperature of a secondary battery with a charging rate SOC and a charge/discharge state taken into account are provided. A method may include a method of estimating an internal temperature (T) of a secondary battery for a vehicle, which includes a change determination process to be repeatedly performed and an internal temperature estimation process to be repeatedly performed.

Abstract: A heat dissipation structure including a plurality of heat dissipating members, and a support plate for supporting the heat dissipating members. Each of the heat dissipating members includes a plurality of cushion members each having a hollow or a solid shape, and a heat conduction sheet covering an outer surface of the cushion members. The support plate includes a plurality of grooves for supporting the heat dissipating members in a direction orthogonal to a longitudinal direction of the heat dissipating members. Each of the grooves is a curved recess portion formed in a thickness direction, opened to the side of the heat dissipating member, formed to have a radius of curvature larger than a radius of curvature of the heat dissipating member, and to have a depth smaller than a circular conversion diameter of the heat dissipating member, and a battery provided with the heat dissipating structure.