Abstract: A client request directed to a web site or other service hosted by a distributed pool of servers is processed by a client agent associated with the client. The client agent intercepts the client request and routes it to a particular one of the servers in the pool. The client agent bases its routing decision on address information regarding the individual servers of the pool and performance data regarding processing of previous client requests directed to the service. The address information may be retrieved by the client agent from a response to an initial client request directed to the service. The performance data may include response times for servicing previous client requests directed to the service, and the client agent may route the client request such that an average response time of multiple requests to the service is minimized.

Abstract: A processor architecture having an accumulator register file with multiple shared read and/or write ports. Depending on the instruction, each port can be used to communicate with a different data source or destination.

Abstract: A method of forming a multi-layered dual-doped polysilicon structure that minimizes Boron penetration into the n+ polysilicon during formation of the p+ polysilicon. The method of the present invention also reduces the migration of Boron (p+ gate dopant) from the p+ polysilicon and the migration of Arsenic and/or Phosphorous (n+ gate dopant) from the n+ polysilicon during subsequent fabrication processing steps. The present invention is also directed to a semiconductor device having a gate dopant barrier that minimizes gate dopant penetration and migration.

Abstract: Memory test hardware is provided for generating signals for testing a first memory array and a second memory array. The first memory array and the second memory array may be any two of main memory array, a spare memory array, and reconfiguration memory array, or the apparatus may be adapted for testing all three memory arrays. The memory test hardware may include a controller for generating control signals, a data generator coupled to the controller for generating data signals, and an address generator coupled to the controller for generating address signals. The test device may further include an output data evaluator and repair unit for receiving signals from the main memory array and the spare memory array and for detecting faults in those arrays.

Abstract: An integrated circuit includes a memory cell that stores a data bit corresponding to one of a low and a high voltage. A memory element is coupled to a data node for storing the data bit and to an inverse data node for storing an inverse of the data bit. At least one write-access port has a write-access switch having an input terminal coupled to a data input line, an output terminal coupled to the data node, and a control terminal coupled to a write control line for switching the write-access switch on or off to provide a write-data bit from the data input line to the write-access port. A preset switch is employed which has a first terminal coupled to one of the data node and the inverse data node, a second terminal coupled to a voltage source sufficient to cause the data node to store a logic-1 data bit when the preset switch is on, and a preset control terminal for switching the preset switch on or off to preset the memory cell before a write operation is coupled to a preset control line.

Abstract: A variable resistor, a method of manufacturing the same and a voltage bias circuit that incorporates at least one variable resistor. In one embodiment, the variable resistor includes: (1) a substrate including a doped region having an inherent resistance, (2) a controllable switch formed in the substrate, electrically coupled to the doped region and having a control terminal and (3) a controller, coupled to the control terminal, that toggles the controllable switch to modify a current flow through the doped region and thereby vary a resistance of the variable resistor.

Abstract: A differential optical signal receiver includes an interference-rejecting circuit to provide enhanced interference signal rejection. The differential optical signal receiver includes a differential optical signal detector for detecting a received differential optical signal and converting it to a differential electrical signal. An interference-rejecting differential electrical circuit, including a common source load, processes the differential electrical signal so as to reject any electrical interference signal other than said differential electrical signal.

Abstract: The specification describes a recessed chip IC package in which the IC chip is bonded to a silicon translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The thermal mismatch between the silicon translator and conventional printed wiring board materials is addressed by using an interposer which is essentially a ball grid array of plated-through holes that transfers the interconnect pattern from the translator to the printed wiring board. The interposer may have a composition with a coefficient of thermal expansion (CTE) that lies between the CTE of silicon and the CTE of the board material. It may also be provided with holes or slots for additional stress relief.

Abstract: An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad.

Abstract: Enhanced Internet service is provided over an ISDN line by eliminating from the D-channel any packets that will introduce unacceptable delay in packets transmitted over the B-channel. The enhancement is achieved by segregating the packets between the B-channels and the D-channel based on the stream to which the packets belong. Furthermore, instead of bonding together both B-channels and the D-channel, only the B-channels may be bonded to each other, while the D-channel is kept independent. To do so, instead of using MLPPP over the combination of both B-channels and the D-channel, as in the prior art, MLPPP is used over only both B-channels, while data that is separately directed to the D-channel employs another protocol, e.g., PPP. Advantageously, the number of protocols used to transmit the information over the D-channel may be reduced, resulting in a higher bandwidth for applications. The bandwidth of the D-channel can be dynamically throttled by an access server.

Abstract: The mobile radio communication system includes a plurality of base stations and call hand over units controlling which of the base stations services a call from a mobile station. When deciding whether to hand over a call from a first base station to a second base station, both serving microcells, the call hand over units hand the call over to a third base station, serving a macrocell, based on a duration of the call regardless of changes in radio coverage of the second base station. Also, the hand over units decide whether to hand over a call from a macrocell base station to a microcell base station based on a length of time the mobile station has been within a coverage area of the microcell base station regardless of changes in radio coverage of the microcell base station.

Abstract: A planar lightguide circuit having a grating coupler to backward couple a elected wavelength from among a plurality of optical signals. A cascaded arrangement of such couplers provides multiplexing or demultiplexing. In its simplest form, a planar lightguide circuit has in close proximity on a substrate first and second planar lightguides having differing effective indices of refraction in a first region. Preferably, the lightguide having the higher effective index of refraction parallels in dose proximity in the first region the lightguide having the lower effective index of refraction, the latter propagating a plurality of multiplexed signals. Typically, this relationship of effective indices of refraction is provided by differences in widths of the lightguides rather than by differences in material composition or differences in layer thicknesses. Optionally, all inputs and outputs have appearances at a common edge of the substrate.

Abstract: A booster for amplifying the signal of a mobile unit of a cellular telephone system. The booster includes a level determination device which produces a reference level based on a power level of a signal received from the mobile unit. The level determination device includes a step voltage circuit which produces a step voltage based on the power level of the signal received from the mobile unit. The step voltage is supplied to a resulting voltage circuit which produces a resulting voltage based on the step voltage, the resulting voltage suitably providing a reference level for the booster.

Abstract: In accordance with the invention, a plurality of high thermal conductivity bodies are bonded to relatively hot spots of a component-populated substrate surface to provide thermal conduction from the surface to an overlying thermal plane. The high conductivity bodies can be configured for pick-and-place application and self-aligned in solder bonding. Receiving solder pads on the substrate facilitate low thermal resistance solder bonding and self-alignment. In a preferred embodiment the bodies are rectangular parallelpipeds with bifurcated bonding surfaces.

Abstract: A system for transmitting data over an erasure channel. A data block is divided into coarse and fine segments. The coarse segment is encoded using an error-correcting encoding process. The fine segment and the encoded coarse segment are combined and divided into packets, and the packets are transmitted over the erasure channel. When the data is received, the coarse segment is decoded. If data packets were lost during transmission, the coarse segment is reconstructed as the received data block. If no packets were lost, the fine segment is combined with the coarse segment and the entire data block as originally transmitted is reconstructed. For large numbers of packets, the system invention can achieve any point within the capacity region of an erasure channel.

Abstract: This invention relates to a system and method for economically locating an ESD event with a reasonable degree of accuracy. It performs this function using a binary approach in which one or more binary ESD locator boxes are used. Each of these binary ESD locator boxes incorporates two antennas and performs the function of determining which of these antennas receives the ESD signal first. This determination establishes the ESD event as occurring to one side of a planar surface. By incorporating one or more additional binary ESD locator boxes, the system can determine whether an ESD event occurred within a two dimensional area or within a three dimensional area.

Abstract: A method of shallow trench isolation by forming a trench in a semiconductor device comprises the steps of forming an oxide layer; forming a mask layer; anisotropically etching the mask layer; forming a second oxide layer; forming a cap layer; forming rounded end caps adjacent the mask; and transferring the rounding of the caps to the top corners of the trench. The oxide layer is formed over a substrate of the semiconductor device. The mask layer is formed over the oxide layer. The mask layer is then anisotropically etched to form the mask and an opening in the mask. The opening in the mask exposes the substrate, and the width of the opening is greater than the width of the trench. Blanket etching the cap layer forms the rounded end caps. The rounded end caps are adjacent to the mask on opposite ends of the opening, and the distance between the end caps is about equal to the width of the trench. The trench is formed by plasma etching the trench.

Abstract: An arrangement for cooling an electronic assembly includes a circuit board having a primary circuit board portion and a secondary circuit board portion integrally secured to the primary circuit board portion. The arrangement also includes an enclosure member secured to the circuit board so as to create a fluid tight barrier of a compartment defined at least in part by the enclosure member. The arrangement further includes a first electronic component secured to the primary circuit board portion such that the first electronic component is located within the compartment. The arrangement also includes a second electronic component secured to the secondary circuit board portion such that the second electronic component is located outside of the compartment. The arrangement also includes a liquid disposed within the compartment such that the liquid is in a heat exchange relationship with the first electronic component.

Abstract: A retainer for a circuit board test probe includes a unitary member in which the test probe is inserted. The retainer may then be plugged into a desired opening in a test fixture plate, with a circumferential bead on the retainer and a circumferential groove in the plate opening providing a snap-in feature. Inward compression of the retainer moves the bead out of the groove to allow the retainer to be removed from the plate opening.

Abstract: An invalid mobile telephone call made within the service area of a vendor monitored by a vendor computer is detected by RF fingerprinting or the like results in transmission of a kill-call command over a TCP/IP network to a kill-call server that is interfaced with a mobile service center through a data link interface. The kill-call server determines whether the kill-call command is valid and, if so, then it transmits a message tear down request over the data link interface to an executive cellular processor which, if the kill-call capability is active, conveys a call termination message to the associated administrative call processing database node to effect the call termination.