Abstract: An electrical insulator for providing insulation between electrical contacts includes an injection molded housing. The housing includes a plurality of apertures adapted to receive the electrical contacts. Electrical contacts are inserted into the apertures and are installed utilizing ultrasonic welding.

Abstract: In a call center (100) of a business, if it is determined (314-318 or 320) during the handling of a call involving a party who is a customer of the business that the party is at risk of being lost as a customer to the business, an identifier of the party, such as ANI, is captured (300) and stored (322) along with an "at risk" indication. The determination may be made either automatically by detecting (314-318) that the party terminated the call while on hold, or manually (320) by the agent handling the call or a service observer whereupon the agent or observer pressed an "at risk" feature button (112) on their terminal (105, 110).

Abstract: A novel and unique method, apparatus and programmed storage medium for approximating large data distributions of a database in order to allow a user to accurately analyze the entire data distribution using a limited amount of memory space in a reasonable amount of time. The approximation is based on partitioning the data domain into a number of regions, approximating each region using any well-known technique, and composing the errors of approximation to optimize suitable criteria for approximating the entire data distribution.

Abstract: In practical WDM systems, the maximum SMSR for each channel does not necessarily occur where dP.sub.out /dI.sub.tune =0. In fact, for most channels the maximum SMSR occurs at values of tuning current where this first derivative in not zero. In accordance with one aspect of the invention, a wavelength stabilized optical transmitter includes a DBR laser and a feedback loop for controlling the center wavelength of the laser, characterized in that the transmitter also includes a memory in which are stored the non-zero values of dP.sub.out /dI.sub.tune where the SMSR is a maximum for each of a multiplicity of different channel wavelengths and further includes a controller responsive to the stored values for delivering to the laser a level of tuning current that maximizes the SMSR for a particular channel wavelength.

Abstract: Methods of using an adiabatic Y-branch digital optical modulator provide a substantially chirp-free modulator by changing the refractive index of only a first output branch of the modulator in response to a modulating signal. A second output branch of the modulator, where no refractive index change is induced, is used as the modulator output. The frequency chirp in this Y-branch modulator is negligible because the modulator output waveguide branch experiences little or no refractive index change and, therefore, little or no phase shift in operation. Substantially all of the phase shift occurs in the waveguide branch where the refractive index change is induced. According to a further embodiment, one or both of the output branches are comprised of one or more tapered waveguide sections.

Abstract: The present invention provides a method for generating a path delay fault test for sequential logic circuits along a desired signal path implementing a two rated speed clocking scheme. Although initialization is accomplished at a reduced clock speed, two functional clock cycles are required to fully activate the desired signal transition along the selected signal path lying between designated source and destination flip-flops. Importantly, prior to the second functional clock cycle that activates the signal transition, a first functional clock cycle attempted at the rated clock speed is used to initialize at least the source flip-flop. In so doing, the automatic test equipment (ATE) that applies the test vectors is allowed to ramp-up to the rated clock speed prior to having to critically apply at the rated speed the required test vectors so as to launch the desired signal transition.

Abstract: The invention is a photodetector device and a lightguide circuit incorporating the device. The photodetector device includes a semiconductor region for absorbing light which is incident on an edge surface of the device. The region above the absorbing region is narrow at the edge and fans out in the direction of light propagation in the device.

Abstract: A subterranean outside plant telecommunications equipment enclosure system including a substantially water-tight containing capsule slidably and rotatably received within a vertical underground sleeve. The capsule is selectively positionable into a first upwardly projecting position with respect to the sleeve and a second storage position within the sleeve. The system provides easy access for servicing and prevents binding of telecommunications cables connected to the capsule.

Abstract: A user accesses the Internet through a hybrid data communications system architecture in which upstream service is provided via the local loop of the public switched telephone network (PSTN) and downstream service is provided via a cable television (CATV) network. The Cable Modem Data Termination system (CMTS) includes a routing table. Upon detection of a CATV service interruption, the CMTS re-routes IP traffic destined for a destination IP address (IP1) associated with the user to a different IP address, or endpoint, as a function of the routing table. In this instance, the different IP address is associated with equipment that provides downstream IP service to the user via the local loop of the PSTN.

Abstract: The NEG output of the Booth encoding circuit and the multiplicand input are gated so as to minimize switching activity in the multiplier without adding any delay to the critical path thereof. Advantageously, power consumption in the multiplier is significantly reduced, e.g., on the order of 90%, when multiplication is in fact not being performed. Additionally, by changing the structure of the last XOR gate of the partial product generation circuit, the need to gate the multiplicand input can be eliminated. Advantageously, this eliminates the extra circuitry which would otherwise be required to gate the multiplicand input, thus reducing cost. Furthermore, additional power savings may be achieved by efficiently resynchronizing the multiplicand input with the Booth encoded input to the partial product circuit.

Abstract: A line driver amplifier is implemented by employing amplifier stages including a plurality of output transistors and a corresponding plurality of auxiliary amplifiers. The output transistor and auxiliary amplifier pairs are connected in parallel. Each of the auxiliary amplifiers includes a built in voltage offset, beginning with an auxiliary amplifier having the smallest voltage offset to the auxiliary amplifier having the largest offset. The individual auxiliary amplifiers maintain their corresponding output transistors in an OFF state so long as the overall amplifier input signal has a magnitude less than the auxiliary amplifier offset voltage level. When the input signal magnitude level is equal to or greater than the offset voltage level of an auxiliary amplifier, that auxiliary amplifier turns its corresponding output transistor to an ON state.

Abstract: The FPGA has an array of programmable logic cells (PLCs) surrounded by a ring of programmable input/output cells (PICs). In one embodiment, the pads of each pair of adjacent PICs, as well as internal routing resources of each of the two PICs, are programmably connected to a single global-signal spine, and the spine is programmably connected directly to only half of the perpendicular branches. Each of the branches can then connect to the cells in two adjacent rows/columns of the array to provide a global signal to any of the cells in the array while only using a branch per every two rows/columns of the device. The reduced number of spine-to-branch connections reduces the capacitive loading on the spines, thereby increasing the speed at which global signals can be transmitted. In addition, sharing spines between adjacent PICs reduces the number of spines in the FPGA by half, thereby providing additional layout space for other resources.

Abstract: A call center for routing of a call from a user to one of a plurality of agent stations of an organization, comprises: an interactive graphical display of information relating to the organization, the display for showing status information of at least one agent station; a device for enabling a user to select an agent station from the display; and, a device for effecting a communications link between the caller and the agent station. Further included is a device for receiving information about the organization and updating the graphical display of information.

Abstract: There is disclosed a loop counter reload circuit loads an initial count value into a counter and a shadow register. A count value output from the counter is changed by a predetermined displacement resulting in a changed count value. The count value from the shadow register is loaded into the counter if the changed count value has reached a predetermined reference value, and otherwise the changed count value is loaded into the counter.

Abstract: An n by m array of lenses layer where n is greater than 1 and m is greater than 1 is disposed on a combination of layers comprised of a first walk-off layer, a first non-reciprocal rotator layer, a first half-wave plate layer, a second half-wave plate layer, a second walk-off layer, a second non-reciprocal rotator layer, and a mirror layer. A method of forming optical p by q structures, where p is greater than 1 is provided. An n by m array of lenses layer where n is greater than 1 and m is greater than 1 is disposed on a combination of layers. The combination of layers is formed of the layers described above. An n by m structure comprising the array of lenses and the combination of layers is formed which is then divided into p by q structures having a p by q array of lenses layer, where p is greater than 1. Preferably p by 1 optical circulator strips are formed. Preferably all layers are formed by lithographic methods. The n by m array of lenses can be formed by reactive ion etching.

Abstract: There is provided an integrated exclusion filter and pressurizing device which prevents leakage of unfiltered fluid across the interface area between a rotating filtering apparatus and non-rotating bulkhead. The exclusion filter utilized is of the type which utilizes Boundary Layer Momentum Transfer methodology to achieve filtration, and which includes a cylindrical stack of substantially flat annular plates. A pressurizing device is utilized downstream from the exclusion filter to repressurize filtered fluid and direct the filtered fluid toward the interface area. Either all the filtered fluid or only a portion may be repressurized, and some of the filtered fluid may be directed toward the bulkhead itself to aid pressurization by creating a local stagnation region. The pressurizing device may utilize flow diverting vanes in a housing, including blowers, pumps, compressors, and fans.

Abstract: A finite impulse response filter uses rotating tap weights that are connected in turn to a succession of sample/hold (S/H) cells in each of which is held a separate successive sample of an analog balanced signal being filtered for an interval long enough to tap to each tap weight in one rotation. Each of the S/H cells is a switched-current memory cell and includes a primary negative feedback transconductance differential amplifier and a primary pair of storage capacitors and a secondary positive feedback transconductance differential amplifier and a secondary pair of storage capacitors. Charge injection errors created in each primary amplifier are replicated in an associated secondary amplifier and used to cancel these errors to provide higher fidelity samples for summing for forming the output of the filter. The tap weights are provided by binary-ratioed resistors provided by transistors of binary-ratioed transconductances.

Abstract: The present invention provides an antenna interlock system comprising an upper housing and a lower housing. The upper housing has first and second interlock tabs disposed along its interior wall, which correspond to third and fourth interlock tabs disposed along the interior wall of the lower housing, the interlock tabs each having an aperture shaped to closely receive the antenna unit. The interlock tabs are disposed relative to each other such that when the upper and lower housings are assembled together, the apertures in the interlock tabs together define a pathway for receiving the antenna unit, and such that when the antenna unit is inserted through the antenna opening and into the receiving apertures, the antenna unit and the interlock tabs hold the upper and lower housing together.

Abstract: A component design tool extracts a parameter associated with a component defined in a model of a physical system. The design tool discretizes the component and generates a matrix representative of a specified parameter. By subdividing the matrix into a hierarchy of submatrices and iteratively compressing and blending the submatrices, the design tool produces a compressed matrix. The compressed matrix is efficiently solved using iterative techniques. From the solution of the matrix, the design tool calculates the specified parameter.

Abstract: A differential amplifier for amplifying the difference between first and second input signals and producing therefrom a differential output signal. The differential amplifier includes first and second transistors connected to a common DC current source and receiving, at the transistor gate terminals, the respective first and second input signals. Each transistor has a common mode voltage associated therewith. A voltage control circuit generates control signals that are applied to the backgate terminals of the transistors to calibrate the differential output voltage and to adjust the common mode voltages of the transistors.