Abstract: A reconfigurable DC-DC converter including a controller is disclosed which automatically adjusts the mode of operation (buck mode or boost mode) depending on the system requirements and is able to achieve the maximum efficiency and the lowest inductance current. The method of switching between buck and boost mode allows the converter to operate to 100% duty cycle for buck mode and 0% duty cycle for boost mode. This maximizes efficiency since the buck-boost mode of operation is eliminated and improves the stability and reliability of the system. A converter output voltage is processed and compared to a control voltage to generate buck and boost comparator output signals. The buck and boost comparator output signals are provided to control logic, which generates switch control signals, which are provided to the DC-DC converter to establish buck mode, boost mode, or pass-through mode.

Abstract: An apparatus having a substrate with an inductor, a first die and a second die is disclosed. The first die may be (i) mounted on the substrate, (ii) configured to vary a frequency of a signal in the inductor, and (iii) fabricated with multiple first masks. The second die may be (i) mounted on the substrate, (ii) configured to excite the signal, and (iii) fabricated with multiple second masks. A particular one of the first masks generally has several designs that customize the first die to several configurations respectively. A particular one of the second masks may have several designs that customize the second die to several configurations respectively. The first die, the second die and the inductor may form a voltage-controlled oscillator. A selected first design and a selected second design generally establish multiple performances of the voltage-controlled oscillator.

Abstract: An apparatus having an amplifier and a correction circuit is disclosed. The amplifier may be configured to amplify an intermediate signal to generate an output signal. The amplifier is generally a microwave frequency power amplifier. The correction circuit may be configured to (i) generate a control signal based on a plurality of characteristics of the amplifier, and (ii) adjust a plurality of phases of a plurality of pulses in a pulse burst to generate the intermediate signal. The adjusting may be in response to the control signal. The pulse burst is generally received in an input signal. The phases of the pulses as adjusted in the intermediate signal generally cancel a plurality of phase errors induced by the amplifier in the pulses.

Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to an intermediate signal. The first circuit may be implemented using a first transistor type. The second circuit may be configured to generate the intermediate signal in response to (i) an input signal and (ii) a feedback of the output signal. The second circuit may be implemented using a second transistor type. The output signal is an amplified version of the input signal while maintaining linearity.

Abstract: A method for single signal transmit/receive module amplifier switching control is disclosed. Step (A) of the method may receive a control signal through a single pin of a circuit. The control signal may alternately conveys (i) a receive mode and (ii) a transmit mode. Step (B) may generate a transmit signal in a disabled state in response to the control signal transitioning from the transmit mode to the receive mode. The transmit signal in the disabled state is generally configured to disable a transmit amplifier. Step (C) may generate a receive signal in an enabled state a receive delay time after the control signal transitions from the transmit mode to the receive mode. The receive signal in the enabled state is generally configured to enable a receive amplifier. The receive delay time may allow the transmit amplifier to switch off before the receive amplifier switches on.

Abstract: An apparatus having a substrate, a first die and a second die is disclosed. The substrate may include a circuit having an inductance. The first die may be (i) mounted on the substrate, (ii) connected to the circuit and (iii) configured to control a frequency of an oscillation of a signal in the circuit. The frequency is generally varied by adjusting a voltage in the first die. The second die may be (i) mounted on the substrate, (ii) connected to the circuit and (iii) configured to excite the signal. The apparatus generally forms a voltage-controlled oscillator.

Abstract: An integrated circuit includes a first circuit and a second circuit. The first circuit may be configured to generate a plurality of complementary outputs based upon a plurality of inputs, a first control signal, and a second control signal, where the plurality of inputs is received as a serial data stream. The second circuit may be configured to generate one or more pairs of complementary output signals and a plurality of open-drain outputs in response to a third control signal, a fourth control signal, a fifth control signal, and a sixth control signal. A first complementary output of each pair of complementary output signals has a higher current capability than a second complementary output of each pair of complementary output signals.

Abstract: An apparatus includes a cascode amplifier and an electrostatic discharge (ESD) protection circuit. The cascode amplifier includes a common source device and a common gate device. The electrostatic discharge (ESD) protection circuit includes a device channel coupled between a drain and a gate of the common gate device. The device channel provides a short circuit between the drain and gate of the common gate device when the cascade amplifier is unbiased.

Abstract: A method for creating step connectors in a test fixture is disclosed. The method generally includes steps (A) and (B). Step (A) may form the connectors in a plurality of regions of a board by reducing a thickness of a metal outside the regions by a distance. Each region generally corresponds to a respective one of a plurality of pads of a package of a device under test. The distance may be measured normal to the board. The distance generally provides a clearance between the board and the package sufficient to make physical and electrical contact between the connectors and the pads. Step (B) may form a plurality of traces on the board. Each trace may (i) be made of the metal and (ii) intersect a respective one of the regions.

Abstract: An integrated circuit including a first circuit, a second circuit, a third circuit, a first complementary pair of transistors, and a second complementary pair of transistors. The first circuit may be configured to generate a first input signal in response to a first control input signal. The second circuit may be configured to generate a first output signal and a second output signal in response to the first input signal and a bias signal. The third circuit may be configured to generate the bias signal in response to a bias input signal. The first complementary pair of transistors may be configured to drive a first series output of the integrated circuit in response to the first output signal. The second complementary pair of transistors may be configured to drive a first shunt output of the integrated circuit in response to the second output signal.

Abstract: An apparatus having an input transmission line, a plurality of amplifiers and an output transmission line is disclosed. The input transmission line may include a plurality of first inductors configured to receive an input voltage. The amplifiers may be configured to generate a plurality of intermediate currents by amplifying a plurality of intermediate voltages at a plurality of first nodes between the first inductors. The output transmission line generally includes a plurality of second inductors configured to generate an output current at an output node by combining the intermediate currents. Each of a plurality of second nodes connected to the second inductors may transfer a plurality of the intermediate currents. Each of the second inductors generally has a different one of a plurality of inductance values.

Abstract: An apparatus having an active device, a plurality of traces and one or more areas is disclosed. The active device may have a channel layer. A buffer layer is generally disposed between the channel layer and a substrate. A parasitic layer may be formed at an interface between the buffer layer and the substrate. The traces may be connected to the active device. The areas are generally proximate at least one of (i) the active device and (ii) at least two of the traces from which the parasitic layer is removed.

Abstract: An apparatus having a bonding pad and a conductor is disclosed. The bonding pad may be formed in a conductive layer of an integrated circuit. The bonding pad generally has (i) a bond region, (ii) an interface edge sized to match a transmission line and (iii) a tapered region between the bond region and the interface edge. The interface edge may be narrower than the bond region. The tapered region generally has a non-rectangular shape that spans from the bond region to the interface edge. The conductor may be bonded to the bond region. The conductor is generally configured to exchange a signal with the bond region. The signal may be in a microwave frequency range.

Abstract: An apparatus having a detector and a circuit is disclosed. The detector may be configured to generate a control signal in response to a voltage level of an input signal. The circuit may be configured to (i) connect the input signal to a reference signal with a first impedance in response to the control signal in an asserted state and (ii) connect the input signal to the reference signal with a second impedance in response to the control signal in a deasserted state. One or more transistors in the circuit are generally biased to an off state while the control signal is in the deasserted state.

Abstract: An integrated circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of complementary outputs based upon a plurality of inputs, a first control signal, and a second control signal. The plurality of inputs may be received in parallel in a first mode and as a serial bit stream in a second mode. The second circuit may be configured to generate a plurality of outputs in response to a third control signal and a fourth control signal.

Abstract: An apparatus comprising a first substrate and a second substrate. The first substrate has disposed thereon a first feature. The second substrate has disposed thereon a second feature. The first feature is configured to interlock with the second feature such that the first substrate and the second substrate are aligned by the first and the second features within a predefined accuracy.

Abstract: A semiconductor device including a plurality of source pads, a plurality of drain fingers, a plurality of gate fingers, a drain combiner connected to the plurality of drain fingers, and a gate combiner connected to the plurality of gate fingers. The plurality of source pads generally comprises a pair of end source pads and one or more inner source pads. Each end source pad is configured to have added inductance. Each of the drain fingers is generally disposed between two of the plurality of source pads. Each of the gate fingers is generally disposed between a respective source pad and a respective drain finger.

Abstract: An apparatus comprising a power amplifier and a control circuit. The power amplifier may be configured to generate an output signal in response to an input signal and a control signal. The control circuit may be configured to present (i) a bias signal as the control signal during un-regulated conditions and (ii) a power down voltage as the control signal when one or more predetermined design parameters are exceeded. The magnitude of the control signal may be configured to dynamically adjust a power level of the output signal. The power down voltage may be generated by sampling the input signal.

Abstract: An apparatus comprising an RF circuit, a converter circuit, an amplifier, and a delay circuit. The RF circuit may be configured to generate (i) an output signal and (ii) a first intermediate signal, in response to (i) an input signal and (ii) a control signal. The converter circuit may be configured to generate a second intermediate signal in response to the first intermediate signal. The amplifier may be configured to generate a third intermediate signal in response to the second intermediate signal. The delay circuit may be configured to generate the control signal in response to the third intermediate signal. The RF circuit may generate the output signal having a flattened response by providing pulse shaping in response to the control signal.

Abstract: An apparatus comprising a first filter, a second filter, a third filter, and a fourth filter. The first filter may comprise a low pass filter having a first bandwidth and configured to present a first output signal in response to an input signal received at an input port of the apparatus. The second filter may comprise a high pass filter having a second bandwidth and configured to present a second output signal in response to the input signal received at the input port of the apparatus. The third filter may comprise a low pass filter having a third bandwidth and configured to present a third output signal in response to the second output signal. The fourth filter may comprise a high pass filter having a fourth bandwidth and configured to present a fourth output signal in response to the second output signal.