Abstract: An apparatus comprising an integrated circuit, an interconnect layer within said integrated circuit, and one or more connections. The integrated circuit may be configured to provide an electrically measurable interconnect pattern by enabling one or more of a plurality of components. The one or more connections may each configured to enable a respective one of the components. The connections may be programmable while the apparatus is part of a wafer. The interconnect pattern may be configured to identify the apparatus after the apparatus has been manufactured.

Abstract: An apparatus comprising an amplifier and a switch network. The amplifier may be configured to generate a plurality of output signals in response to an input signal. The switch network may be configured to provide (i) a first path when a power signal is not present and (ii) a second path when said power signal is present. The first path may activate a first of the plurality of output signals. The second path may activate all of the plurality of output signals. An impedance may be connected to the amplifier only when the first path is activated.

Abstract: An apparatus comprising one or more series transistor network elements and a plurality of shunt circuits. The series transistor network may be configured to generate an output signal in response to (i) an input signal, (ii) a first bias signal, and (iii) a plurality of variable impedances. The plurality of shunt circuits may each be configured to generate a respective one of the variable impedances in response to a second bias signal. The output signal may have an attenuation that is equal to or less than the input power. The amount of the attenuation may be controlled by the first bias signal and the second bias signal. The series transistor elements and the plurality of shunt circuits may be configured as two or more transistors each having two or more gates.

Abstract: An integrated global positioning system (GPS) receiver and cellular transceiver module including (i) a printed circuit board substrate, (ii) a cellular multiband antenna disposed on the printed circuit board substrate, (ii) at least one first integrated circuit disposed on the printed circuit board substrate for processing signals from and signals to the cellular multiband antenna, (iii) a GPS antenna attached to the printed circuit board substrate, (iv) at least one second integrated circuit disposed on the printed circuit board substrate for processing signals from the GPS antenna and the at least one first integrated circuit, and (v) an electrical connector disposed on the printed circuit board substrate for establishing a data communication path between the at least one first and the at least one second integrated circuits and an electronic system of a vehicle, where the GPS receiver and cellular transceiver module is capable of being integrated into the electronic system of the vehicle.

Abstract: A monolithic microwave integrated circuit (MMIC) compatible broadside-coupled transformer including (i) a first transmission line, (ii) a second transmission line, and (iii) a third transmission line. The first and the second transmission lines generally form the broadside-coupled transformer. The third transmission line is generally connected in series with the broadside-coupled transmission line forming a ground return path of the broadside-coupled transformer.

Abstract: An amplifier output impedance matching configuration including a first impedance transformer and one or more second impedance transformers. The first impedance transformer receives input signals from a power amplifier and generates output signals to a load. The one or more second impedance transformers are connected between the first impedance transformer and the load through which the output signals are passed.

Abstract: A process for fabricating a semiconductor device. The process including (a) growing a channel layer on a buffer layer, (b) growing a barrier layer on the channel layer, (c) epitaxially growing a quaternary etch-stop layer on the barrier layer, (d) growing a first contact layer on the quaternary etch-stop layer, (e) growing a second contact layer on the first contact layer, (f) etching portions of the second contact layer to reveal a first recess surface, and (g) etching portions of the first contact layer to reveal a second recess surface. The second contact layer may be a highly doped contact layer. The second recess surface generally forms a gate region. The first and the second contact layers have a first etch rate and the quaternary etch-stop layer has a second etch rate in a chosen first etch chemistry.

Abstract: A process for fabricating a semiconductor device. The process includes (a) growing an n-channel layer of gallium arsenide (GaAs) on a buffer layer, (b) growing a barrier layer on the re-channel layer, (c) epitaxially growing a first etch-stop layer on the barrier layer, (d) growing a first contact layer of wide band-gap material on the first etch-stop layer, (e) epitaxially growing a second etch-stop layer on the first contact layer, (f) growing a second contact layer on the second etch-stop layer, where the second contact layer is a highly doped material, and (g) selectively etching portions of the first contact layer, the second etch-stop layer, and the second contact layer to form a gate region.

Abstract: A method for fabricating a transistor and the resulting transistor is disclosed. The method generally includes steps (A) to (E). Step (A) may form a high mobility layer. The high mobility layer is generally configured to carry a two-dimensional electron gas. Step (B) may form a planar layer on the high mobility layer. Step (C) may form a barrier layer on the planar layer. Step (D) may form a doped layer on the barrier layer. The doped layer is generally a low bandgap III-V semiconductor. Step (E) may form a gate in contact with the doped layer. The gate may be separated from both a source and a drain by corresponding ungated recess regions. The high mobility layer, the planar layer, the barrier layer, the doped layer, the source, the gate and the drain are generally configured as a pseudomorphic high electron mobility transistor.

Abstract: A control circuit and a conversion circuit. The control circuit may be configured to generate an analog control signal in response to a digital control signal. The conversion circuit may be configured to generate a capacitance signal in response to the analog control signal.

Abstract: Various embodiments are directed to providing constant phase digital attenuation. In one embodiment, a digital attenuator circuit (100) comprises an input node (102) to receive an input signal to be attenuated, an output node (104) to output an attenuated signal, a reference loss path (106) between the input node (102) and the output node (104), and an attenuation path (108) between the input node (102) and the output node (104). The reference loss path (106) comprises switching elements and matching circuitry to improve Voltage Standing Wave Ratio (VSWR), and the attenuation path (108) comprises switching elements and attenuating circuitry to attenuate the input signal when the digital attenuator circuit (100) is switched from a reference loss state to an attenuation state. An effective phase length of the reference loss path (106) and an effective phase length of the attenuation path (108) may be equalized to provide a constant phase when the digital attenuator circuit (100) is switched between states.

Abstract: An apparatus includes an antenna (e.g., a monopole), a first load, and a second load. The antenna, which extends substantially along an axis, has a first end and a second end. The first load is coupled to the antenna at the first end, while the second load is coupled to the antenna between the first end and the second end. Both the first and second loads are symmetrical with reference to the axis. The apparatus is arranged to operate in at least two frequency bands, such as the AMPS band from about 824 MHz to 894 MHz and the PCS band from about 1850 MHz to 1990 MHz.

Abstract: A combined matching and harmonic rejection circuit with increased harmonic rejection provided by a split resonance for one or more of the capacitive or inductive elements of the circuit. At a fundamental frequency, the circuit comprises an inductive series arm with capacitive shunt arms. The capacitance of a shunt arm may be provided by two or more parallel paths, each having a capacitor and an inductor in series so that, in addition to providing the effective capacitance necessary for impedance matching at the fundamental frequency, two separate harmonics represented by the series resonances of the parallel paths are rejected. In this manner, an extra null in the circuit's stop-band may be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency.

Abstract: A circulator/isolator housing is provided that includes body and a plurality of slots within the body configured to receive therethrough inserts having magnetic permeability. The housing further includes a plurality of receiving portions within the body corresponding to the plurality of slots and configured to maintain a position of the inserts.

Abstract: A single-die multi-band switch includes a plurality of transmitter ports and a plurality of receiver ports, any one of which is selected to be connected to an antenna port. At least some of these switching topologies use a branched or cascaded switching system in order to reduce signal insertion loss. It is preferred that the individual switching elements be field effect transistors. The switching topologies employed include series-connected groups of transistors and interdigitated FETs.

Abstract: A PIN diode comprising an N-type substrate comprising a cathode of the PIN diode and having an intrinsic layer disposed upon the N-type substrate and having a top surface a P-type material disposed upon the top surface of the intrinsic layer comprising an anode of the PIN diode and a N-type material disposed over the sidewall of the cathode and over the sidewall and a portion of the top surface of the intrinsic material that is not occupied by the anode, wherein a horizontal gap is defined between the anode and the cathode through the intrinsic material, the gap being variable in width and/or the horizontal gap is less than the thickness of the intrinsic layer.

Abstract: A switch includes at least two signal ports in series with a series FET connected therebetween, and a shunt path having an FET, whereby an input bias is applied to a gate on the series FET and to a drain on the shunt FET. In one embodiment, the switch includes a control signal input, an FET connected in series across the first port and the second port, the series FET having a gate coupled to the control signal input, and a shunt path provided by an FET, the shunt FET having a drain coupled to the control signal input and to the gate of the series FET, whereby a single control signal is applied to both the series FET and the shunt FET, via the control signal input, in order to turn the series FET on and simultaneously turn the shunt FET off and, conversely, in order to turn the series FET off and simultaneously turn the shunt FET on.

Abstract: A circulator/isolator housing is provided that includes body and a plurality of slots within the body configured to receive therethrough inserts having magnetic permeability. The housing further includes a plurality of receiving portions within the body corresponding to the plurality of slots and configured to maintain a position of the inserts.

Abstract: A series-shunt switch is provided. The switch includes a PIN diode having an input electrical terminal, an output electrical terminal and a thermal terminal. The thermal terminal is configured to provide continuity of diode thermal ground with respect to a circuit thermal ground node.

Abstract: A diode having a first semiconductor region of a first polarity and a second semiconductor region of an opposite polarity at least partially surrounding the first semiconductor region. A metal contact coupled to the second semiconductor region at least partially surrounding the first semiconductor region. The diode offers improvements in switching speed.