Abstract: Systems, methods, circuits, and apparatus for managing data transfer in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first circuit, a data bus coupled to the first circuit, and a precharging circuit coupled to the data bus. The precharging circuit is configured to precharge the data bus to have a predetermined voltage before data is transferred through the data bus. The first circuit is conductively coupled to the data bus by applying a control voltage to the first circuit. The control voltage is determined based on the predetermined voltage.

Abstract: A data search method for a memory device is provided. The data search method includes: based on a recorded compression mode, vectoring a search data to generate a search data vector, and based on the recorded compression mode, compressing the search data and a plurality of objects in a database; setting a search condition; searching the objects of the database by the search data vector to determine whether the search data is matched with the objects of the database; and recording and outputting at least one matched object of the database, the at least one matched object matched with the search data.

Abstract: Systems, devices, methods, and circuits for managing status output are provided. In one aspect, a semiconductor device includes: a memory array configured to store data and a circuitry coupled to the memory array and configured to execute a read operation in the memory array and output a read packet based on a result of the execution of the read operation. The read packet includes readout data and error information associated with the readout data. The error information is indicated by at least one of an error code or one or more secure codes in the read packet.

Abstract: Systems, devices, methods, and circuits for managing reference currents in semiconductor devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in sets of memory cells and circuitry coupled to the memory cell array. Each set of one or more sets of memory cells in the memory cell array is associated with a respective reference current, and memory cells in sets associated with different reference currents have different threshold voltage distributions. The circuitry is configured to: determine information associated with a reference current for a set of memory cells in the memory cell array based on a memory address corresponding to the set, generate the reference current based on the information associated with the reference current for the set, and sense one or more memory cells in the set based on the reference current.

Abstract: A sensing module, a memory device, and a sensing method are provided to perform a read operation so that the un-programmed/programmed state of a memory cell is identified. The sensing module includes a sensing amplifier and a current sink, and both are electrically connected to the memory cell. The sensing amplifier generates a sensing current and identifies the un-programmed/programmed state of the memory cell accordingly. The current sink receives a reference current being equivalent to the summation of the sensing current and a cell current flowing through the memory cell. The reference current is constant, and the sensing current is changed with the cell current. The cell current is generated based on a high read voltage and a low read voltage applied to the memory cell. The sensing current is higher if the memory cell is un-programmed, and the sensing current is lower if the memory cell is programmed.

Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a programming operation, programming a plurality of threshold voltages of a plurality of switches on a plurality of string select lines and a plurality of ground select lines as a first reference threshold voltage, and programming a plurality of threshold voltages of a plurality of dummy memory cells on a plurality of dummy word lines as being gradually increased along a first direction or a second direction, and the threshold voltages of the dummy memory cells being higher than the first reference threshold voltage; wherein the first direction being from the string select lines to a plurality of word lines and the second direction being from the ground select lines to the word lines.

Abstract: A memory array is provided and including a plurality of bit lines and a plurality word lines; a plurality of memory cell units, arranged at cross points of the plurality of bit lines and the plurality of word lines; a bit line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of bit lines; a word line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of word lines; and a voltage clamper circuit, provided in at least one of the word line switch circuit and the bit line switch circuit.

Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

Abstract: A memory device, such as three dimension AND Flash memory, including a plurality of word line decoding circuit areas, a plurality of common power rails and a plurality of power drivers is provided. The word line decoding circuit areas are arranged in an array, and form a plurality of isolation areas, wherein each of the isolation areas is disposed between two adjacent word line decoding circuit areas. Each of the common power rails is disposed along the isolation areas. The power drivers respectively correspond to the word line decoding circuit areas. Each of the power drivers is disposed between each of the power driving circuit areas and each of the corresponding isolation areas, wherein each of the power drivers is configured to provide a common power to the word line decoding circuit areas.

Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

Abstract: A data recovery method is applied to a memory device which has a target memory cell, a target word line and an adjacent word line adjacent to the target word line. The target word line is connected to a gate of the target memory cell. The adjacent word line is connected to a gate of an adjacent memory cell, and the adjacent memory cell is adjacent to the target memory cell. In the data recovery method, a first program voltage is applied to the target memory cell through the target word line, and a second program voltage is concurrently applied to the adjacent memory cell through the adjacent word line.

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Abstract: A thermally compensated circuit includes a first adjustable circuit, like an adjustable current source, to produce a first adjustable signal, such a reference current. The circuit includes a second adjustable circuit to produce a second adjustable signal, such as a reference voltage. Circuitry responsive to the first and second adjustable signals produces an output, such as a clock signal. A tunable circuit in the first adjustable circuit and a tunable first element of the second adjustable circuit set an operating characteristic, such as a clock period, of the output to a target level at a first temperature. A tunable second element of the second adjustable circuit sets the operating characteristic of the output signal at the target level at a second temperature. Tuning of the second tunable element at the second temperature does not substantially change the operating characteristic of the output signal at the first temperature.

Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.

Abstract: A storage device for generating an identity code and an identity code generating method are disclosed. The storage device includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores a plurality of first data and the first data have a plurality of bits. The second storage circuit stores a plurality of second data and the second data have a plurality of bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, selects a first portion of the first data according to the first sequence, reads the first portion of the first data from the first storage circuit to form a target sequence and outputs the target sequence to serve as an identity code.

Abstract: An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a first circuit to generate a temperature-dependent voltage (TDV) that is dependent on an operating temperature of the integrated circuit, and a second circuit to generate a plurality of temperature reference voltages, based on or more codes. One or more comparator circuits compare individual ones of the plurality of reference voltages with the TDV, to generate one or more comparison signals that are indicative of the operating temperature of the integrated circuit.

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. In one aspect, a chiplet system includes multiple integrated circuit devices electrically connected together. The integrated circuit devices include an integrated circuit device including: an integrated circuit, a plurality of first type bonding pads electrically connected to the integrated circuit and electrically connected to at least one other of the integrated circuit devices, and one or more second type bonding pads electrically isolated from the at least one other of the integrated circuit devices. At least one of the plurality of first type bonding pads is configured to be electrically connected to a corresponding one of the one or more second type bonding pads.

Abstract: Memory devices are implemented within a vertical memory structure, comprising a stack of alternating layers of insulator material and word line material, with a series of alternating conductive pillars and insulating pillars disposed through stack. Data storage structures are disposed on inside surfaces of the layers of word line material at cross-points of the insulating pillars and the layers of word line material. Semiconductor channel material is disposed between the insulating pillars and the data storage structures at cross-points of the insulating pillars with the layers of word line material. The semiconductor channel material extends around an outside surface of the insulating pillars, contacting the adjacent conductive pillars on both sides to provide source/drain terminals.

Abstract: Systems, methods, circuits, and apparatus for managing multi-block operations in memory devices are provided. In one aspect, a memory device includes a memory cell array including at least two blocks, a bit line coupled to a string of memory cells in each of the at least two blocks respectively, a common source line (CSL) coupled to strings coupled to the bit line in the at least two blocks, and a circuitry configured to perform a multi-block operation in the memory cell array by at least one of: forming a first current path from the bit line through the strings to the CSL coupled to a ground to discharge a capacitor associated with the bit line that is pre-charged, or forming a second current path from the CSL coupled to a supply voltage through the strings to the bit line to charge the capacitor that is pre-discharged.