Abstract: A first communication device in a first wireless network determines a transmit power for transmitting a first packet during a spatial reuse opportunity corresponding to a transmission in a second wireless network. Determining the transmit power includes using a spatial reuse parameter, indicative of an acceptable interference level in the second wireless network, included in a second packet transmitted by a second communication device in the second wireless network. The first communication device generates the first packet to include information to indicate to a third communication device, that is an intended receiver of the first packet, to not transmit an acknowledgment of the first packet according to a normal acknowledgment procedure during the spatial reuse opportunity.

Abstract: This disclosure describes systems and methods for detecting motion based on channel correlation in wireless communication signals. A receiver at a first wireless communication device is capable of wirelessly communicating with a second wireless communication device. The first wireless communication device is configured to receive from the second wireless communication device via two or more subcarriers a first packet and a channel correlation for the first packet across the two or more subcarriers. Control circuitry is configured to estimate a channel energy difference for the receiver based on the channel correlation for the first packet. A motion detection decision is then made based on the estimated channel energy difference.

Abstract: During operation of an analog filter having one or more filter stages is configured to operate in a first configuration. Configuring the analog filter to operate in the first filter configuration includes configuring one or both of i) a filter response of the analog filter and ii) a filter bandwidth of the analog filter. A first set of one or more direct current (DC) offset correction codes corresponding to the first filter configuration are retrieved from a memory. The one or more DC offset correction codes in the first set are converted to one or more first analog DC offset correction signals. While operating the analog filter configured in the first configuration, the one or more first analog DC offset correction signals are applied to the one or more filter stages of the analog filter.

Abstract: In aspects of acknowledgement options for downlink multi-user transmission, a wireless network system includes an access point that can communicate a downlink multi-user transmission soliciting acknowledgement from one or more station devices. The access point can receive an association request or an operation mode change request frame from one or more of the station devices, and determine an acknowledgement option for each of the station devices that communicate the request to the access point. The access point can then use a multi-user transmission mode or a single user transmission mode for each of the station devices based on the acknowledgement option determined for each of the respective station devices.

Abstract: Techniques create a semiconductor layout comprising a resistor structure having a defined baseline sheet resistance. The semiconductor layout includes a resistor marker layer over the resistor structure. A sheet resistance matching estimate is performed to ascertain a difference between the baseline sheet resistance and a resultant sheet resistance if the resistor structure were to be manufactured using a manufacturing process. A mask generating algorithm is generated based on the difference effective to achieve a sheet resistance of the resistor structure that is closer to the baseline sheet resistance rather than the resultant sheet resistance. The mask generating algorithm enables one or more masks to be generated to modify the resistor structure relative to the resistor marker layer.

Abstract: A media content converter, for converting media content into network packets, includes logic circuitry, a header generator and a multiplexer. The logic circuitry is configured to partition the media content into payloads for the network packets. The header generator configured to generate packet headers for the network packets, by populating with data a plurality of header fields according to a predefined header format. The multiplexer is configured to stream a sequence of the network packets for transmission over a communication network, by combining the generated packet headers from the header generator with the corresponding payloads from the logic circuitry.

Abstract: Embodiments described herein provide circuitry employing an inductor having enhanced circuit area usage. The circuitry includes an inductor having a first loop and a second loop adjoining the first loop to form a figure-eight configuration. The circuitry further includes a circuit component disposed at least partially inside an area defined by at least one of the first loop and the second loop. The inductor has an intersection portion between the first loop and the second loop. An input node is located proximate to the intersection portion, the input node having a first extension disposed inside the first loop. An output node is located proximate to the intersection portion. The output node has a second extension disposed inside the second loop. At least a first capacitor is coupled to the input node and the second extension, and at least a second capacitor coupled to the output node and the first extension.

Abstract: Systems and methods for carrier sensing and symbol timing in a multiple-antenna communication system are provided. A wireless receiver receives two or more signals from two or more antennas, respectively. A set of column vectors comprising time samples obtained from each of the received signals at the two or more antennas are generated. A multiple-antenna eigen-combining (MAEC) vector is computed based on the set of column vectors. The respective received signals are multiplied with a corresponding combining coefficient of the MAEC vector to obtain a respective weighted signal. A combined signal is generated by adding the respective weighted signals and carrier sensing and symbol timing is performed on the two or more received signals based on the combined signal.

Abstract: Provided is a method in a device under configuration (DUC) for communicating with a remote device over a wireless local area network. The method comprises transmitting a beacon to a remote device, providing a first security key to the remote device using first security measures, authenticating the remote device using second security measures, receiving encrypted secrets from the remote device, and obtaining network access using the secrets. Also, provided is a method of providing network access information over a wireless network. The method comprises identifying a device under configuration (DUC) from information contained in a beacon transmitted by the DUC, retrieving a public KEY from the DUC, authenticating the DUC using first security measures, encrypting secrets, and transmitting encrypted commands to the DUC.

Abstract: A receiver device receives a signal via a communication channel, the signal (i) having been transmitted by a transmitter device, and (ii) corresponding to a pseudorandom bit sequence (PRBS). The receiver device correlates the received signal with a known signal to generate a correlation signal. The known signal includes the PRBS. The receiver device identifies one or more characteristics of the correlation signal, and determines one or more parameters of the communication channel using the identified one or more characteristics of the correlation signal. The receiver device i) uses the one or more parameters corresponding to the communication channel to process subsequent signals received via the communication channel, and/or ii) communicates the one or more parameters to the transmitter device to prompt the transmitter device to preprocess subsequent signals to be transmitted via the communication channel by the transmitter device.

Abstract: Disclosed are scan flip-flops (SFFs) that reduce the dynamic power consumption of a system-on-chip (SOC) that incorporates them. Each SFF includes a master latch and a slave latch, each having a driver, a feed-forward path and a feedback path. Each SFF further includes at least one shared clock-gated power supply transistor, which is controlled by either a clock signal or an inverted clock signal to selectively and simultaneously connect a voltage rail to both the driver from one latch and the feedback path of the other latch. The different SFF embodiments have different numbers of shared clock-gated power supply transistors and various other different features designed for optimal power and/or performance. For example, the different SFF embodiments have different types of slave latch drivers; different types of transistors; and/or different types of master latch drivers (e.g., a single-stage, multiple clock phase-dependent driver or a multi-stage, single clock phase-dependent driver).

Abstract: A method for communication, including, in a Physical Layer (PHY) transceiver, selecting a transmission bitrate from a plurality of transmission bitrates, for transmitting over a media interface bits received from an external device. The received bits are processed by generating, using a framing and encoding scheme that depends on at least the selected transmission bitrate, frames having a common frame length among the framing and encoding schemes. The frames are encoded to produce code words of a predefined Forward Error Correction Code (FEC) code, using a single FEC encoder that accepts a number of bits for encoding equal to the frame length. Sub-units of the code words are mapped into symbols using one of at least two mapping schemes that employ different voltage amplitude levels to define a transmission symbol, the mapping scheme being selected according to the selected transmission bitrate. The symbols are transmitted over the media interface.

Abstract: Embodiments described herein provide echo cancellation power saving management at a cable transceiver. An echo response signal having a first number of signal components is obtained, via an echo cancellation filter. At a first iteration for calculating a first accumulative echo power, a respective echo tap that corresponds to the first iteration is identified. The first accumulative echo power is calculated for the respective iteration by summing powers of outputs from a last echo tap to the respective echo tap. It is then determined whether the first accumulative echo power, exceeds a pre-determined echo power threshold. If the first accumulative echo power exceeds the pre-determined echo power threshold, a first turn-off indication is sent to the echo cancellation filter to turn off all echo taps including and between the last echo tap to the first echo tap.

Abstract: Aspects of the disclosure provide an apparatus that includes a transceiver circuit and a processing circuit. The transceiver circuit is configured to transmit and receive wireless signals. The processing circuit is configured to generate a request frame using an extended control frame format to indicate an enhanced fine timing measurement (EFTM) based range measurement to a second apparatus, cause the transceiver circuit to transmit, when a transmission opportunity (TXOP) is granted to the apparatus, wireless signals carrying the request frame to start the EFTM based range measurement that exchanges null data packets with the second apparatus, and determine a round trip time based on departure and arrival timing information of the null data packets.

Abstract: Some embodiments described herein provide a method for transmitting an access request via a flexible register access bus. An access request may be received to access resource on an integrated circuit. The access request may be translated to a request packet having a data format compliant with the flexible register access bus. A routing path may be determined for the request packet based on a target register associated with the request packet. The request packet may be transmitted via the routing path to the target register. Information within the request packet may be translated to a local access protocol for the target register. Access to the resource may then be obtained via the target register based on the local access protocol.

Abstract: Aspects of the disclosure provide an apparatus that includes a receiving circuit and a processing circuit. The receiving circuit is configured to receive a satellite signal transmitted from a satellite. The satellite signal carries navigation bits that are transmitted with a navigation bit length. The processing circuit is configured to construct aiding navigation bits based on aiding ephemeris and almanac information that are provided by an aiding source other than the satellite signal. Further, the processing circuit is configured to strip the navigation bits from the satellite signal based on the aiding navigation bits to generate a post-stripping signal, and perform an integration on the post-stripping signal.

Abstract: A short-reach data link receiver includes an edge detector configured to generate a pulse on an edge of a data input, a first clock-data recovery path coupled to an output of the edge detector for recovering a clock and data from the output of the edge detector, a second clock-data recovery path coupled to the output of the edge detector for recovering the clock and data from the output of the edge detector, and a controller configured to alternate between the first and second clock-data recovery paths to recover the clock and data using one of the paths while calibrating the other path. The controller may swap the paths whenever calibration of one path is completed. That may include beginning calibration of the next path immediately after swapping of the paths. Alternatively, power consumption may be reduced by delaying calibration of the next path after swapping of the paths.

Abstract: A memory device structure includes a wafer substrate and a magnetic tunnel junction (MTJ) positioned above an upper surface of the wafer substrate. The MTJ includes a first magnetic layer, a second magnetic layer laterally adjacent the first magnetic layer, and a nonmagnetic layer interposed between the first and second magnetic layers, wherein the first magnetic layer, the nonmagnetic layer and the second magnetic layer comprise a substantially vertical layer stack that extends along a first direction that is substantially perpendicular to the upper surface of the wafer substrate. A first contact is electrically coupled to the first magnetic layer and a second contact is electrically coupled to the second magnetic layer.

Abstract: Systems and methods for decoding a product code is provided. The system comprises a media, a first buffer, a second buffer, and a decoder. The media stores a plurality of codewords of a first code of the product code. The first buffer temporarily stores at least one codeword that has failed to be decoded. The second buffer temporarily stores soft information to be used in decoding. The decoder is configured to decode the plurality of codewords, determine if a first count of the at least one failed codeword exceeds a designed maximum number of codewords recoverable using the decoding method. In response to determining that the first count does not exceed the predefined threshold, the decoder iteratively process each failed codeword of the at least one failed codeword with the soft information, and attempt to decode at least one of each failed codeword that has been iteratively processed.

Abstract: In the disclosed design systems and methods, a schematic diagram includes nets and, connected to at least some nets, single-pin first and second imaginary devices. On any given net, a first imaginary device is associated with a tracking group property of the net (where nets in the same tracking group are in-phase) and a second imaginary device is associated with a voltage property of the net. A design layout generated based on the schematic diagram includes: net shapes representing the nets and, on net shapes that represent nets connected to the imaginary devices, tracking group and voltage labels corresponding to the tracking group and voltage properties. Net shape placement within the design layout and design rule checking are performed according to design rules that dictate placing net shapes with the same tracking group label together and further dictate minimum allowable spacing requirements depending upon the tracking group and voltage labels.