Abstract: A packet parsing engine comprises a DMEM configured to store packet data; one or more registers configured to store parsing instructions or parse results; and one or more arithmetic logic units configured to parse the packet data based on the parsing instructions and to derive the parse results. The engine may be one engine of a plurality of engines configured to access a shared memory, and the engine may be configured to receive data from the shared memory or to send data to the shared memory. The DMEM may be divided into subsections, and at least one of the one or more registers may be divided into subsections, and the subsections may be configured such that while a DMEM subsection and its corresponding register subsection is parsing packet data for a first packet, one or more other subsections load packed data or unload parse results for a second packet.

Abstract: System and method of data routing according to a hierarchical scheduling process. Incoming data traffic is allocated to various queues of a buffer. A scheduling tree has a top level for queues, a bottom level for egress ports, and a plurality of intermediate levels corresponding to different granularities with respect to service categories. Each queue is assigned to a particular node in each intermediate level of the scheduling tree. The scheduling tree traverses through multiple scheduling stages from the bottom to the top level to select a winner node in each level based on a variety of fairness and differentiating variables. A queue associated with the winner nodes in various levels is selected for outgoing transmission at the selected egress port. Priority information is dynamically propagated from upper nodes to lower nodes such that a subsequent scheduling process uses the updated priority information.

Abstract: System and method of write deskew training for ×4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.

Abstract: Aspects of the disclosure provide an operational transconductance amplifier (OTA) having an output stage. The output stage includes a first amplifier path configured to drive a first output current from a first power supply and a first resistor coupled between the first power supply and a source terminal of a first transistor in the first amplifier path. The first resistor is configured to improve a linearity of the OTA.

Abstract: An amplifier includes a first switch and a second switch each having a first terminal and a second terminal. The first terminals of the first and second switches respectively communicate with a first tank circuit and a second tank circuit. The second terminal of the second switch communicates with the second terminal of the first switch. A first capacitance having a first terminal connected directly to (i) the second terminal of the first switch and (ii) the second terminal of the second switch. A second terminal of the first capacitance is connected directly to a first input voltage of the amplifier. A first load is connected across (i) the first terminal of the first switch and (ii) the first terminal of the second switch. The amplifier generates a first output across the first load.

Abstract: Methods to identify a fluorescent lamp among multiple fluorescent lamps include: receiving input to a circuit including multiple fluorescent lamps operated by corresponding multiple control signals, each fluorescent lamp configured to output radio frequency (RF) signals in response to receiving a detection signal, the input to identify which first control signal is provided to a first fluorescent lamp; in response to receiving the input, providing a first discovery signal in place of each control signal provided to each fluorescent lamp, one fluorescent lamp at a time; determining that the first fluorescent lamp outputs RF signals; and identifying the control signal that was replaced with the detection signal that caused the first fluorescent lamp to output the RF signals.

Abstract: Method to identify a current drawn by a fluorescent lamp in a circuit. Methods include receiving a voltage supplied to a fluorescent lamp drawing a current in response to the voltage, digitally sampling the voltage at a sampling frequency and associating a first time stamp with a voltage value representing one of a maximum or minimum value in observed voltage, receiving the current after receiving the voltage, digitally sampling the current at the sampling frequency and associating multiple second time stamps with a corresponding multiple current values, identifying a second time stamp, a difference between the first time stamp and the second time stamp being within a threshold, and identifying a current value associated with the second time stamp as the current drawn by the fluorescent lamp.

Abstract: Some of the embodiments of the present disclosure provide an apparatus comprising a command cancellation channel (CCC) including a plurality of stages, the CCC configured to receive a first memory address of a sequence of memory addresses and a corresponding first modification command, determine that at least a first stage of the plurality of stages includes the first memory address and a corresponding second modification command, and erase the first memory address or cancel the second modification command while shifting the first memory address and the second modification command from the first stage to a second stage. Other embodiments are also described and claimed.

Abstract: A system and method of extending a standard bridge to enable execution of logical bridging functionality are disclosed. In some implementations, a logical bridge may assign source logical port information to a data packet based on characteristics of the data packet, employ the source logical port information to learn the source address and to forward the data packet to a logical egress port, and map the logical egress port to a physical egress port at which the data packet is to be egressed. A tunnel interface may optionally be applied to a data packet upon egress.

Abstract: A resynchronization device for an Ethernet network device with a transmitter and a receiver includes a detector that detects faulty code groups received by the receiver. A counter counts the faulty code groups that are detected by the false carrier detector during a predetermined period. A resynchronization trigger asserts a resynchronization signal if the counter exceeds a predetermined threshold during the predetermined period. The faulty code groups include false carriers, which include non-idle code groups other than frame delimiters. Alternately, the faulty code groups include idle code groups that match idle code groups generated by the transmitter of the local network device.

Abstract: Method and apparatus for modifying standard VLAN tags to perform network packet switching. The method includes receiving a data packet at a port of a network switch and determining whether the data packet has a virtual local area network (VLAN) tagged frame. If the received data packet has a VLAN tagged frame, then the method further includes modifying and encoding fixed portions of the VLAN tag frame with switching information. The switching information includes information for central management of data packet flow through the network switch.

Abstract: A hash function is applied to a set of data to generate a hash. A first subset of the hash is used to lookup an entry in a lookup table for a forwarding database. A second subset of the hash is used to identify, within the entry, data comprising an offset. The offset is applied to a location identified in the forwarding database by the first subset of the hash to determine an entry in the forwarding database. Optionally, the lookup mechanism is used in conjunction with one or more other forwarding databases. A method of updating the forwarding database within the double hash lookup framework is also described.

Abstract: Methods and apparatus are provided for receiving a first signal and generating an output signal indicative of radio data system (“RDS”) information. A receiver circuit of the invention can include mixer circuitry, lowpass filter circuitry, downsampler circuitry, and decoder circuitry. Advantageously, the receiver circuit can operate entirely within the digital domain, promoting interoperability with digital frequency modulation (“FM”) demodulator circuitry.

Abstract: Among other disclosed subject matter, a magnetic disk controller can include an index detecting unit to detect an index of the magnetic disk, an error check code generating unit to, after the index detecting unit detects the index, generate a first error check code for first write data based on the first write data and a first physical address of a first sector subsequent to the detected index, and a writing control unit to cause the first error check code generated by the error check code generating unit, the first write data and the first physical address to be written into a second sector subsequent to the first sector.

Abstract: A built-in-self-test (BIST) system for testing a memory that includes a scheduler module that generates a first test algorithm based on a set of operational codes. Each operational code defines a test operation to be performed by the first test algorithm on the memory. The BIST system also includes an execution module that applies the first test algorithm to the memory.

Abstract: Among other disclosed subject matter, a magnetic disk controller includes an interface that receives and transmits data to be written into a magnetic disk. The magnetic disk controller includes a first buffer and a second buffer each of which temporarily stores data that is to be written into at least one sector of the magnetic disk. The magnetic disk controller includes an encoding unit that encodes the data stored in any of the first buffer and the second buffer into data representing a signal to be applied to the magnetic disk. A data width M between the encoding unit and the first and second buffers is at least equal to twice a data width N between the interface and the first and second buffers.

Abstract: A device previously configured as a registrar and that has established an independent ad-hoc network is automatically discovered by another device also previously configured as a registrar. To form an ad-hoc wireless network between these two devices, each device periodically enters a scanning mode to scan for and intercept beacons transmitted by the other device. Upon such interception, one of the devices becomes an enrollee in accordance with a predefined condition and in response to a user selected option. Subsequently, the enrollee modifies its beacons to include an attribute, such as the MAC address, associated with the other device. After intercepting the modified beacon, the remaining registrar prompts it user to decide whether to allow the enrollee to join the registrar's network. If the user responds affirmatively, a handshake is performed between the two devices and a subsequent attempt is made by the enrollee to join the registrar's network.

Abstract: Methods, circuits, architectures, and systems for error detection in transmitted data. The method generally includes the steps of (i) partitioning the unit of digital data into one or more full data lines and a remainder, wherein each of the full data lines comprises a predetermined number of data blocks, each of the data blocks has a first fixed length, the predetermined number is an integer of at least 2, and the remainder has a length less than the predetermined number times the first fixed length; (ii) if the remainder contains at least one data bit, adding to the remainder a padding vector having a length sufficient to generate a padded data line having the predetermined number of data blocks; and (iii) performing error checking calculations on the full data lines and the padded data line. The present invention reduces the chip area and power consumption, while improving system performance.

Abstract: Testing devices at various locations on a die may be used to determine one or more properties of the locations. For example, a testing device including an oscillator such as a ring oscillator at a location may be used to determine a silicon quality, temperature, and/or voltage at the location.

Abstract: Systems and techniques for producing a signal with a known phase relationship to a source clock at an output of an indeterminate circuit element such as a clock divider. The systems and techniques may be used to allow circuit test data to be accurately compared with simulation data.