Abstract: Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a zero-padded data portion, then checking the data and zero-padded data portions for a transmission error. The circuit generally includes a circuit to detect non-data; a circuit configured to replace non-data with a zero-pad vector; and a circuit to detect a transmission error in data and zero-padded data portions of information, and combine the zero-pad vector with a remaining data portion to form the zero-padded data portion. The present invention enables a single error detection circuit to detect errors, thereby reducing chip area, increasing efficiency, and reducing power consumption.

Abstract: A circuit and related method of monitoring performance of an integrated circuit is provided comprising: using a variable oscillator that has an oscillation time period that varies within an expected range with variations in one or more of process, voltage or temperature to provide a signal that causes a count of a first counter to change at rate proportional to an oscillation frequency of the variable oscillator; using a clock source that has a frequency that substantially does not vary with variations in one or more of process, time or voltage to cause a count of a second counter to change at rate proportional to an oscillation frequency of the clock source; setting the second counter to start a count from a start; determining when the first counter has counted a reference count; and providing as a circuit speed, a value indicative of a count value produced by the second counter at about the moment when first counter finishes counting the count interval.

Abstract: A circuit generates a qualified data read strobe signal from a start burst signal and a bidirectional data strobe signal in a DDR memory control module. The circuit includes a delay module that receives the start burst signal and that generates a delayed start burst signal. An enable signal generator receives the delayed start burst signal and generates an enable signal. A first circuit generates the qualified data read strobe signal based on the enable signal and the bidirectional data strobe signal.

Abstract: A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.

Abstract: The present disclosure includes systems and techniques relating to FIFO queue memory. In general, in one implementation, a queue memory receives and stores information and supports first-in-first-out read and out-of-order read operations with information shifting within the memory relative to a read operation. The queue memory can include a write pointer that increments upon a write operation and decrements upon the read operation, a read pointer that identifies an oldest read entry of the queue memory when the read operation is a first-in-first-out read and that identifies a selected entry of the queue memory when the read operation is an out-of-order read, and a multiplexer operative to select entries of the queue memory responsive to the read pointer.

Abstract: A protocol governing the operation of an ad-hoc WLAN enables each device in the WLAN to be configured as a registrar and/or an enrollee. Accordingly, each device is configurable to support both the registrar as well as enrollee modes of operations. In response to a time-driven user action, the device may be configured to enter into a registrar mode or an enrollee mode. While in the registrar mode, the device enters into an aggressive beaconing phase by setting its beacon contention window to a relatively very small value. The aggressive beaconing increases the probability of the discovery of the registrar by the enrollees. Optionally the device may prompt the user to select between a registrar and an enrollee mode of operation by displaying the option on an LCD panel.

Abstract: A digitally controlled oscillator circuit is provided that comprises a ring oscillator including multiple inverters; multiple digitally controlled capacitors (DCCs), each coupled to apply a digitally controllable amount of capacitance to an output of a different one of the inverters; and control circuitry operable to change an amount of capacitance applied to each inverter during operation of the ring oscillator and to cause the multiple DCCs to apply substantially the same amounts of capacitance to each of the inverter throughout operation of the ring oscillator.

Abstract: Resources allocated to a group of ports include a plurality of storage regions. Each storage region includes a committed area and a shared area. A destination storage region is identified for a packet. A packet queuing engine stores the packet in the committed area of the determined destination storage region if it has a first drop precedence value, and if available storage space in the committed area exceeds a first threshold. The packet queuing engine stores the packet in the shared area of the determined destination storage region if the packet is not stored in the committed area, and if available storage space exceeds a second threshold defined by the packet's drop precedence value. If the packet is not stored either in the committed or shared area, it may be dropped.

Abstract: A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.

Abstract: An inverted-phase detector is implemented in a system including a first clock circuit that provides a first clock signal and a delayed clock circuit that outputs an delayed clock signal. A reference circuit outputs a reference signal. A feedback circuit generates a feedback signal that is one of greater than and less than the reference signal when the first clock signal changes state before the second clock signal, and that is the other of greater than and less than the reference signal when the first clock signal changes state after the second clock signal.

Abstract: An embodiment of the present invention offloads the generation and monitoring of test packets from a Central processing Unit (CPU) to a dedicated network integrated circuit, such as a router, bridge or switch chip associated with the CPU. The CPU may download test routines and test data to the network IC, which then generates the test packets, identifies and handles received test packets, collects test statistics, and performs other test functions all without loading the CPU. The CPU may be notified when certain events occur, such as when throughput or jitter thresholds for the network are exceeded.

Abstract: A memory device and method for looking up data corresponding to an input address includes a memory lookup module, memory that communicates with the memory lookup module, and content addressable memory (CAM) that communicates with said memory lookup module.

Abstract: A method and computer program for verifying a design of a circuit comprises providing a model of the design; providing a first property for the design, wherein the first property describes a first behavior; checking the model using the first property and an environment of the design starting at a reset state until an example of the first behavior occurs; providing a second property for the design, wherein the second property describes a second behavior; and checking the model using the second property and an environment of the design starting at a state when the example of the first behavior occurs.

Abstract: A digital feedback loop circuit achieves a resolution as good as the intrinsic resolution of the delay element of the circuit, notwithstanding the presence of a feedback counter/divider of integer value N that might otherwise be expected to multiply the minimum resolution by N. Output altering circuitry is used to alter the error feedback signal for M out of every N feedback cycles in such a way that the overall delay over N cycles can be controlled to within the resolution of the delay element. In one embodiment, the output altering circuitry includes a second counter whose maximum value is controllable and that outputs a signal whose value changes after its current maximum value has been reached. In another embodiment, the output altering circuitry includes a lookup table preloaded with sequences of output signals, with the sequence selected by a controller.

Abstract: A method and computer program for verifying a design of a circuit comprises selecting a portion of a model of the design having a plurality of inputs and outputs; providing a property for the design that defines a predetermined behavior of one or more of the outputs; determining whether a stimulus exists that, when applied to the inputs of the portion, can produce a behavior other than the predetermined behavior at the outputs of the portion; when the stimulus exists, determining whether the model of the design of the circuit can produce the stimulus at the inputs of the portion of the model of the circuit; and when the stimulus cannot be produced by the model of the design of the circuit at the inputs of the portion of the model of the circuit, preserving a description of the stimulus for analysis.

Abstract: A method and computer program for testing a design of a circuit comprises providing a model of the design; providing a first property for the design, wherein the first property describes a first behavior; checking the model using the first property and an environment of the design at a reset state until an example of the first behavior occurs; providing a second property for the design, wherein the second property describes a second behavior; and checking the model using the second property and an environment of the design at a state when the example of the first behavior occurs.

Abstract: High resolution digital delay circuits and methods are provided. A multiplexer receives the outputs of first and second delay elements. At least the second delay element is adjustable using a digital control signal. The multiplexer and the first delay element form a first delay loop. The multiplexer, the first delay element and the second delay element form a second delay loop. A logic circuit monitors the number of times (M) that a signal cycles through the first loop. After M reaches a predetermined value (i.e., when the signal is delayed by a predetermined delay), the multiplexer receives a control signal that causes the second loop to close. A signal cycles through the second loop, which provides additional delay. Preferably, the signal cycles through the second loop only once. Generally, this causes the resolution of the delay circuit to be proportional to the minimum delay adjustment of the second delay element.

Abstract: A search engine improves search speed and reduces required memory for a longest prefix matching (LPM) router that routes packets using IP addresses. The search engine includes a first bit vector with set bits corresponding to address ranges. A set bit counter counts the set bits in the bit vector based on a first portion of the address of the a first packet. A first next hop table contains first pointers for each of the set bits. One of the first pointers is selected based on a number of set bits counted by the set bit counter. For longer addresses, the addresses are split into address portions. The search engine includes a trie data structure that has n levels. The n levels of the trie data structure include nodes representing non-overlapping address space.

Abstract: An integrated circuit, having a method therefor, includes a memory including a plurality of memory lines, each memory line including a plurality of data cells each to store a data bit, and a plurality of error-correction (EC) cells each to store an EC bit corresponding to the data bits stored in the data cells of the memory line; an EC input circuit to generate the EC bits based on the corresponding data bits; an EC output circuit including an EC correction circuit to correct errors in the bits read from the data cells of each of the memory lines in accordance with the bits read from the EC cells of the memory line; and a switch including first inputs to receive the EC bits from the EC input circuit, second inputs to receive test EC bits from EC test nodes of the integrated circuit, and outputs to provide either the EC bits or the EC test bits to the memory in accordance with a test signal.

Abstract: Circuitry and methods for an efficient FIFO memory are provided. This efficient FIFO memory has two smaller standard single-port memory banks instead of one large dual-port memory bank, as in typical FIFO memories. Whereas the dual-port memory based FIFO memory can read and write data at the same time, a typical single-port memory based FIFO cannot. In accordance with the invention the operation of the two single-port memory banks are coordinated in order to provide similar or better performance than a dual-port memory based FIFO.