Abstract: A data network including at least one crossbar, wherein each crossbar comprises N ports and a plurality N of devices each associated with and connected to one port of one of the crossbars. Each one port of one crossbar includes an input buffer, a plurality N?1 of port output buffers, a plurality N?1 of fullness sensors, shutoff devices. The input buffer receives messages from the device connected to its port and sends the messages to the other ports of the one crossbar. Each port output buffers corresponds to one of the other ports, wherein each port output buffer receives the messages only from the input buffer of its associated other port. Each fullness sensor is associated with one port output buffer and measures the fullness state of its associated port output buffer.

Abstract: A crossbar for communicating with at least one device, the crossbar comprises N ports. Each one of the N ports comprises a link logic unit to receive messages and data from a respective device, N?1 output buffers each corresponding to another one of the N?1 ports and a port arbiter to select one of the N?1 output buffers to output data to the respective device. The stored data is transferred to the corresponding output buffer of a selected one of the other one of the N ports.

Abstract: A buffer switch comprises a data memory that stores a plurality of data. A cache memory comprises a plurality of FIFO mini-queues each storing a plurality of descriptors each corresponding to a respective one of the plurality of data. An output memory comprises a plurality of output queues. A burst writer simultaneously transfers M ones of the plurality of descriptors stored in a corresponding one of the plurality of mini-queues to at least a corresponding one of the plurality of output queues. The burst writer accesses the output memory, when the output memory is available, once for every M ones of the plurality of descriptors.

Abstract: Testing devices at various locations on a die may be used to determine one or more properties of the locations. For example, a testing device including an oscillator such as a ring oscillator at a location may be used to determine a silicon quality, temperature, and/or voltage at the location.

Abstract: A method of forming a flip chip device comprises providing a semiconductor die having a core area and a periphery area. The periphery area includes an electrostatic discharge (ESD) structure. The semiconductor die including includes at least one power conductor. A substrate having a source of power is provided. A first connection circuit is located within the semiconductor die core area to couple power between the substrate and the semiconductor die power conductor. The ESD structure is electrically coupled to the first connection circuit. The first connection circuit is electrically coupled to the substrate via a conductive bump.

Abstract: A flip chip assembly comprising a semiconductor die having a core area and a periphery area. The periphery area including an ESD structure. The semiconductor die includes at least one power conductor to supply power between the core area and the periphery. A substrate is coupled to the semiconductor die via a plurality of electrically conductive bumps. A first connection circuit is located within the semiconductor die core area to couple power between the substrate and the semiconductor die power conductor. An electrically conductive bump provides a connection between the first connection circuit and the substrate. The ESD structure is coupled to the first connection circuit.

Abstract: A network switch which includes a plurality of output ports, at least one input port and a queuing manager. Each output port has a control unit associated therewith. The input port receives incoming data destined for various ones of the output ports. The queuing manager directs the incoming data to their destination output ports. Each control unit includes an output queue, a fullness/emptiness sensor and a head of line (HOL) mask. The output queue stores the incoming data destined for its associated output port. The sensor senses when the output queue reaches a fullness or an emptiness state. The HOL mask is connected to the output of the sensor and blocks inflow of the incoming data to the output queue when the sensor senses the fullness state and for enabling inflow when the sensor senses the emptiness state.

Abstract: A method and circuit that supplies valid logic values at an end of a transmission line for sampling on high speed interfaces, such as HSTL and SSTL, during reset. The circuit may include operational amplifiers and resistors.

Abstract: A network switch which includes a plurality of output ports, at least one input port and a queuing manager. Each output port has a control unit associated therewith. The input port receives incoming data destined for various ones of the output ports. The queuing manager directs the incoming data to their destination output ports. Each control unit includes an output queue, a fullness/emptiness sensor and a head of line (HOL) mask. The output queue stores the incoming data destined for its associated output port. The sensor senses when the output queue reaches a fullness or an emptiness state. The HOL mask is connected to the output of the sensor and blocks inflow of the incoming data to the output queue when the sensor senses the fullness state and for enabling inflow when the sensor senses the emptiness state.

Abstract: An intregrated circuit includes at least one I/O buffer. This buffer includes a first supply logic portion, connectable to a core voltage supply and an I/O voltage supply, and a second I/O buffer portion adapted to receive an activation signal from the first supply logic portion. The first supply logic portion is modified to act to prevent the output of an activation signal until the core voltage is supplied to the integrated circuit.

Abstract: A sampling device includes a first delay circuit and a second delay circuit in a parallel configuration, where the first delay circuit and the second delay circuit are responsive to a clock signal. A data sampling circuit may use an output of the first delay circuit and an output of the second delay circuit to sample a data signal synchronized with the clock signal. The data signal and the clock signal may be synchronized according to a double data rate (DDR) protocol.

Abstract: A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.

Abstract: A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.

Abstract: A device for writing descriptors, the device including a local memory comprising a multiplicity of mini-queues, wherein each of the mini-queues temporarily stores a plurality of descriptors, wherein each of the descriptors is associated with one of the data packets. Additionally including an output memory comprising a multiplicity of output queues, wherein each of the output queues in output memory is associated with one of the queues in said local memory, and a burst writer which writes N descriptors simultaneously from the mini-queue in the local memory to its associated output queue in output memory.

Abstract: A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL useful for clock synchronizing applications, such as clock recovery elements in transmission/recording channels. The PLL provides in-phase and quadrature signals from a voltage controlled oscillator (VCO) which has two differential transconductors. The second differential transconductor has a positive input coupled to a positive output of the first differential transconductor, a negative input coupled to a negative output of the first differential transconductor, a positive output coupled to a negative input of the first differential transconductor, and a negative output coupled to a positive input of the first differential transconductor. Each differential transconductor has a negative output impedance.

Abstract: An Ethernet controller, for use within an Ethernet network of other Ethernet controller connected together by a bus, is provided. The Ethernet controller includes a plurality of ports including at least one bus port associated with ports connected to other switching Ethernet controllers, a hash table for storing addresses of ports within the Ethernet network, a hash table address control, a storage buffer including a multiplicity of contiguous buffers in which to temporarily store said packet, an empty list including a multiplicity of single bit buffers, a packet storage manager, a packet transfer manager and a write-only bus communication unit. The hash table address control hashes the address of a packet to initial hash table location values, changes the hash table location values by a fixed jump amount if the address values stored in the initial hash table location do not match the received address, and provides at least an output port number of the port associated with the received address.