Abstract: A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.

Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.

Abstract: The preferred embodiments described herein provide a memory device and method for temperature-based control over write and/or read operations. In one preferred embodiment, the temperature of a memory array is monitored, and a write operation to the memory array is prevented in response to the monitored temperature reaching a threshold temperature. In another preferred embodiment, the temperature of a memory array is monitored, and a read operation from the memory array is prevented in response to the monitored temperature reaching a threshold temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Abstract: A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may include the capability to utilize bonding pads on all four sides of an integrated circuit. A lead frame structure may be divided into first and second portions. The first portion may be adapted to receive the stacked integrated circuits and the second portion may include a plurality of conductors. The first portion may also be adapted to couple at least one of the integrated circuits to power and ground conductors on the second portion. In one embodiment, the first portion may include the lead frame paddle and a conductive ring. In another embodiment, the first portion may include first and second coplanar elements.

Abstract: A memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A thin film transistor includes an insulating substrate, an active layer located over the substrate, a gate electrode located over the substrate; and a charge storage region located between the active layer and the gate electrode. The charge storage region includes a tunneling dielectric located adjacent to the active layer, a blocking dielectric located adjacent to the gate electrode and a charge storage dielectric located between the tunneling dielectric and the blocking dielectric. At least one of the tunneling dielectric, the charge storage dielectric and the blocking dielectric comprises a layer having a dielectric constant greater than 3.9, such as a metal oxide layer.

Abstract: The preferred embodiments described herein provide a memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A method to enhance grain size in polysilicon films while avoiding formation of hemispherical grains (HSG) is disclosed. The method begins by depositing a first amorphous silicon film, then depositing silicon nuclei, which will act as nucleation sites, on the amorphous film. After deposition of silicon nuclei, crystallization, and specifically HSG, is prevented by lowering temperature and/or raising pressure. Next a second amorphous silicon layer is deposited over the first layer and the nuclei. Finally an anneal is performed to induce crystallization from the embedded nuclei. Thus grains are formed from the silicon bulk, rather than from the surface, HSG is avoided, and a smooth polysilicon film with enhanced grain size is produced.

Abstract: The preferred embodiments described herein provide a three-dimensional memory cache system. In one preferred embodiment, a modular memory device removably connectable to a host device is provided. The modular memory device comprises a substrate, a cache memory array, a three-dimensional primary memory array, and a modular housing. The cache memory array and the three-dimensional primary memory array can be on the same or separate substrates in the modular housing. In another preferred embodiment, an integrated circuit is provided comprising a substrate, a cache memory array in the substrate, and a three-dimensional primary memory array above the substrate. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A semiconductor device contains a word line, a charge storage region located above the word line, an active layer located above the charge storage region, a patterned etch stop layer located above a first portion of the active layer, and bit lines located over a portion of the etch stop layer and over second portions of the active layer.

Abstract: A memory cell for a two- or a three-dimensional memory array includes first and second conductors and set of layers situated between the conductors. This set of layers includes a dielectric rupture anti-fuse layer having a thickness less than 35 Å and a leakage current density (in the unruptured state) greater than 1 mA/cm2 at 2 V. This low thickness and high current leakage density provide a memory cell with an asymmetric dielectric layer breakdown voltage characteristic. The antifuse layer is formed of an antifuse material characterized by a thickness Tminlife at which the antifuse material is ruptured by a minimum number of write pulses having a polarity that reverse biases diode components included in the memory cell. The average thickness T of the antifuse layer is less than the thickness Tminlife.

Abstract: A semiconductor device, such as an inverted staggered thin film transistor, includes a gate electrode, a gate insulating layer located above the gate electrode, an active layer located above the gate insulating layer and an insulating fill layer located above the active layer. A first opening and a second opening are located in the insulating fill layer, a first source or drain electrode is located in the first opening and a second source or drain electrode is located in the second opening. At least one of the first and the second source or drain electrodes comprise a polysilicon layer and a metal silicide layer.

Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.

Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.

Abstract: A method of selecting numbers of sub-array groups for simultaneous operation to optimize bandwidth biases a number of sub-array groups and compares a circuit state value, preferably voltage, to a reference parameter to determine if the operation can successfully be performed for that number of sub-array groups. The comparison may be repeated with different numbers of sub-array groups biased to find the optimum number of sub-array groups for the operation.

Abstract: Two types of topologically different three-dimensional integrated circuits (for example a 4-layer three-dimensional memory array and an 8-layer three-dimensional memory array) are fabricated from a single set of photolithographic masks. In one example, masks 1-5 are used along with other masks to create the first four levels of memory cells in both a 4-layer memory array and an 8-layer memory array. The 8-layer memory array is completed with masks used to form the top four layers of the array. An integrated circuit identification circuit generates an appropriate circuit identification signal for both types of integrated circuits by sensing whether a conductive path across some or all of the device levels of the integrated circuit is continuous, and then by selecting the appropriate circuit identification signal.

Abstract: A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract: A method of making a silicon-based electronic device is provided. The method includes, for example, the steps of forming a doped silicon layer on a surface of a substrate material and forming an undoped silicon capping layer on the doped silicon layer. The thin “capping” layers of undoped silicon prevent outgassing of the dopants underneath the cap. In this manner, the next deposition of doped silicon is not subject to autodoping by the previous doped silicon deposition.