Patents Assigned to Matsushita Electronics Corporation
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Patent number: 6326792Abstract: A stressing voltage is applied to a dielectric film (step S23). An A-SILC is monitored with stressing time and is plotted on a log-log scale (step S24). A straight line is applied to the plotting, a stressing time at which the line crosses a predetermined value of the A-SILC (a breakdown threshold) is obtained, and the obtained stressing time is predicted as the lifetime of the dielectric film (step S26).Type: GrantFiled: September 16, 1998Date of Patent: December 4, 2001Assignee: Matsushita Electronics CorporationInventor: Kenji Okada
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Patent number: 6320229Abstract: In a semiconductor substrate of a first conductivity type, first and second high-concentration layers of a second conductivity type are formed in spaced relation to each other. A reference voltage is applied to the second high-concentration layer. A conductive layer provides an electrical connection between the first high-concentration layer and an input pad for inputting an input signal to an input circuit or input/output circuit. A first low-concentration layer of the second conductivity type is formed in the region of the semiconductor substrate immediately underlying the first high-concentration layer.Type: GrantFiled: April 29, 1999Date of Patent: November 20, 2001Assignee: Matsushita Electronics CorporationInventors: Toshitaka Uchikoba, Masahiko Sakagami, Akihiro Yamamoto
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Patent number: 6320310Abstract: In an image display apparatus comprising a fluorescent layer formed on the inner surface of a vacuum container, an electron emission source, and a supporting member sandwiched between the fluorescent layer and the electron emission source so that the fluorescent layer and the electron emission source are kept in parallel, a displacement preventing system is provided to prevent displacement of the electron beams emitted from the electron sources caused by the charging of the supporting member. More specifically, the supporting member may be composed of an insulating portion contacting with the electron emission source and a conducting portion contacting with the fluorescent layer. An electrode portion may be provided between the insulating portion and the conductive portion. Electron sources are arranged on the insulating substrate so that the electron beams emitted from the electron sources will be landed on the fluorescent layer with an equal pitch.Type: GrantFiled: September 4, 1998Date of Patent: November 20, 2001Assignee: Matsushita Electronics CorporationInventors: Kanji Imai, Michiaki Watanabe, Hiroshi Aono, Yasuhiko Sakai
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Publication number: 20010041373Abstract: A ferroelectric thin film capacitor has smooth electrodes permitting comparatively stronger polarization, less fatigue, and less imprint, as the ferroelectric capacitor ages. The smooth electrode surfaces are produced by carefully controlled drying, soft baking, and annealing conditions.Type: ApplicationFiled: April 26, 2001Publication date: November 15, 2001Applicant: Matsushita Electronics CorporationInventors: Shinichiro Hayashi, Tatsuo Otsuki
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Publication number: 20010040253Abstract: A gate insulating film composed of silicon oxide and a floating gate electrode composed of polysilicon are formed sequentially on a P-type silicon substrate. A capacitance insulating film composed of silicon oxide and a control gate electrode composed of polysilicon are formed on the floating gate electrode. First spacer films, each composed of silicon oxide and formed over the respective side faces of individual components, and second spacer films, each composed of silicon nitride and formed on the respective first spacer films, are also provided. Even when a high-temperature heat treatment is performed in an oxidizing atmosphere, oxygen is prevented from being supplied to both end portions of the capacitance insulating film and the control gate electrode, which suppresses an increase in thickness of the capacitance insulating film at both end portions thereof.Type: ApplicationFiled: February 26, 2001Publication date: November 15, 2001Applicant: Matsushita Electronics CorporationInventor: Kazuo Sato
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Patent number: 6310800Abstract: A non-volatile semiconductor memory device of the present invention includes, on a semiconductor substrate, a plurality of memory cells arranged in a matrix, a plurality of word lines extending in a row direction, a plurality of source lines extending in the row direction, and a plurality of bit lines extending in a column direction, wherein a plurality of memory cells belonging to a certain row are connected to a first source line among the plurality of source lines, a plurality of memory cells belonging to a row adjacent to the certain row are connected to a second source line among the plurality of source lines, and the first source line is electrically independent from the second source line.Type: GrantFiled: June 26, 2000Date of Patent: October 30, 2001Assignee: Matsushita Electronics CorporationInventor: Keita Takahashi
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Patent number: 6310373Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a C-axis orientation to the final crystal, and results in improved thin-film electrical properties.Type: GrantFiled: August 21, 1995Date of Patent: October 30, 2001Assignees: Symetrix Corporation, Matsushita Electronics CorporationInventors: Masamichi Azuma, Carlos A. Paz De Araujo
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Publication number: 20010031505Abstract: A liquid precursor for forming a thin film of ferroelectric metal oxide in an integrated circuit contains metal oxides in excess of the stoichiometrically balanced amount. When the precursor comprises strontium, bismuth, tantalum and niobium for forming strontium bismuth tantalum niobate, the precursor contains excess amounts of at least one of tantalum and niobium. Capacitors containing thin films of layered superlattice material made from a precursor containing excess tantalum and niobium show good polarizability and low percentage imprint after 1010 negative polarization switching pulses at 75° C., and after 109 negative polarization switching pulses at 125° C.Type: ApplicationFiled: May 19, 2001Publication date: October 18, 2001Applicant: Symetrix Corporation and Matsushita Electronics CorporationInventors: Koji Arita, Shinichiro Hayashi, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
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Publication number: 20010028588Abstract: A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time.Type: ApplicationFiled: June 8, 2001Publication date: October 11, 2001Applicant: MATSUSHITA ELECTRONICS CORPORATIONInventors: Toshio Yamada, Akinori Shibayama
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Publication number: 20010028056Abstract: To provide a method for evaluating chargeup damage caused in the practical fabrication process. Evaluation is carried out based on the electric current flowing between the source and the drain of a MOS transistor of a semiconductor element (1-1) having a wiring layer provided with an antenna effect by installing the semiconductor element (1-1) in the periphery of a practical device installed in a semiconductor substrate and measuring the electric current without attaching a probe to the gate of the semiconductor element (1-1).Type: ApplicationFiled: March 29, 2001Publication date: October 11, 2001Applicant: MATSUSHITA ELECTRONICS CORPORATIONInventor: Masaharu Yamamoto
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Patent number: 6300711Abstract: An indirectly heated cathode that can enhance the withstand voltage and the efficiency of radiating heat from a heater to a tubular sleeve, and a cathode ray tube using such a cathode. The indirectly heated cathode comprises a hot cathode emitting electrons at one end, and a tubular sleeve including a high melting point metal and having a heater inside. A thermal absorption layer is formed on the inside face of the tubular sleeve and the thermal absorption layer contains a boron compound.Type: GrantFiled: August 20, 1998Date of Patent: October 9, 2001Assignee: Matsushita Electronics CorporationInventors: Yoji Yamamoto, Katsuyuki Yamashita
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Publication number: 20010024251Abstract: Without housing a bare chip type liquid crystal driver within a package, to surely shield or absorb the light which reaches the liquid crystal driver so that erroneous display due to the photoelectric effect can be prevented. A light shielding tape 109 is affixed to the top surface of an upper panel 101 of a liquid crystal display panel 10 at an area which is opposite to the mounting area of a liquid crystal driver 107 mounted on the bottom surface of the upper panel 101. The light shielding tape 109 serves to shield the outer light incident on the liquid crystal driver 107. A diffusion sheet 40 composed of a light diffusing area 401 and a light absorbing area 402 located on the outer periphery thereof is arranged below the liquid display panel 10. The light diffusing area 401 serves to diffuse illumination light from a light source 202 to the liquid crystal display panel 10, and the light absorbing area 402 serves to absorb the extraneous light incident on the liquid crystal driver 107.Type: ApplicationFiled: June 7, 2001Publication date: September 27, 2001Applicant: Matsushita Electronics Corporation.Inventors: Mika Gomi, Yoji Inomata
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Patent number: 6294438Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: June 8, 2000Date of Patent: September 25, 2001Assignee: Matsushita Electronics CorporationInventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 6294884Abstract: A vertical deflection circuit for a color picture tube apparatus, which reduces a white horizontal belt-like area that appears near vertical center of a color picture tube screen, caused by the operation of a convergence correction circuit using switching characteristics of a diode. The circuit comprises a vertical deflection yoke and a vertical linearity correction circuit connected to the vertical deflection yoke. The vertical deflection yoke has a vertical deflection coil, a convergence correction circuit using a diode as a switch, and a vertical coma aberration correction coil. An impedance of the vertical linearity correction circuit varies within a range where a vertical deflection current is in the vicinity of 0 A so as to reduce an impedance of the vertical deflection circuit.Type: GrantFiled: April 12, 1999Date of Patent: September 25, 2001Assignee: Matsushita Electronics CorporationInventors: Yukio Uchida, Tomoaki Iwamoto
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Patent number: 6291350Abstract: An ultrasonic transmitting unit transmits an ultrasonic wave to a slurry supply pipe. A polishing slurry is conveyed under pressure from a slurry supply tank to a slurry outlet via the slurry supply pipe and supplied from the slurry outlet to a surface of a polishing cloth. A wafer carrier holding a semiconductor wafer presses a surface of the semiconductor wafer against the surface of the polishing cloth coated with the polishing slurry and moves the semiconductor wafer relative to the polishing cloth to polish the surface of the semiconductor wafer. A discharged slurry flown out of the surface of the polishing cloth is discharged via a discharged slurry pipe. The application of the ultrasonic wave allows abrasive particles agglomerated in the polishing slurry in the slurry supply pipe to be re-dispersed into individual forms in the polishing slurry.Type: GrantFiled: August 3, 1998Date of Patent: September 18, 2001Assignee: Matsushita Electronics CorporationInventors: Shin Hashimoto, Yuichi Miyoshi
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Publication number: 20010021572Abstract: A method for producing a semiconductor device of the present invention includes: heating a first semiconductor layer made of a Group III nitride-based compound semiconductor in gas containing nitrogen atoms; and growing a second semiconductor layer made of a Group III nitride-based compound semiconductor on the first semiconductor layer.Type: ApplicationFiled: December 26, 2000Publication date: September 13, 2001Applicant: Matsushita Electronics CorporationInventors: Kenzi Orita, Masahiro Ishida, Masaaki Yuri
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Publication number: 20010020709Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.Type: ApplicationFiled: March 5, 2001Publication date: September 13, 2001Applicant: Matsushita Electronics CorporationInventors: Keisaku Nakao, Akihiro Matsuda, Yasufumi Izutsu, Toyoji Ito, Takumi Mikawa, Toru Nasu, Yoshihisa Nagano, Keisuke Tanaka, Toshie Kutsunai
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Publication number: 20010020815Abstract: A color cathode ray tube comprises (i) a glass bulb comprising a substantially rectangular panel, on which phosphors of a plurality of colors are arranged, a funnel that is connected to a rear side of the panel, and a neck portion formed at a rear side of the funnel, in which an in-line electron gun for emitting an electron beam is arranged; (ii) a substantially rectangular shadow mask having a plurality of apertures that are arranged in correspondence with the phosphors on the panel; and (iii) a substantially rectangular mask frame having a wall portion that supports opposing skirt portions of the shadow mask. The surface of the shadow mask with the apertures is convex towards the panel. A central portion of the opposing skirt portion is convex in a direction of the tube axis on the side of the electron gun. Processing warps such as wrinkles in the skirt portions of the shadow mask are avoided, and a color cathode ray tube with good color rendition is obtained.Type: ApplicationFiled: May 14, 2001Publication date: September 13, 2001Applicant: Matsushita Electronics CorporationInventors: Katsumi Mitsuda, Hiroo Terada
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Publication number: 20010019874Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.Type: ApplicationFiled: January 24, 2001Publication date: September 6, 2001Applicant: Matsushita Electronics CorporationInventors: Yasuhiro Uemoto, Eiji Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
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Publication number: 20010019530Abstract: A semiconductor laser device is provided which can carry out recording and reproduction with respect to optical disks with different formats. In this semiconductor laser device, a receiving/emitting optics integrated substrate, in which two semiconductor laser elements with different emission wavelengths and a plurality of receiving optics are integrated, is disposed in a case and is sealed with a hologram element. A composite prism is placed on the hologram element. The distances, when measured in air, from the two semiconductor laser elements to a focusing means, for example, a collimator lens are set to be substantially equal. Thus, a small and inexpensive semiconductor laser device can be obtained. In addition, a single collimator lens can be employed, and thus the optical configuration is facilitated.Type: ApplicationFiled: February 26, 2001Publication date: September 6, 2001Applicant: Matsushita Electronics CorporationInventors: Yukio Saitoh, Shoichi Takasuka, Naoki Nakanishi, Hideyuki Nakanishi