Abstract: The invention provides a decoding circuit and a decoding method for a Viterbi decoder. The decoding circuit of the Viterbi decoder includes a branch metric unit, an add-compare-select unit and a path memory unit. The path memory unit includes a data string controller, a trace write-in register array, an idling register array and a decoding register array. In this invention, a run length limited code is used for effectively solving the problem of generating a complicated trellis diagram after the trellis diagram of the Viterbi decoder is subjected to a longitudinal arrangement. In addition, the register array can perform other operations at different times. Accordingly, a high decoding speed of the Viterbi decoder can be achieved without requiring a lot of registers for data processing.

Abstract: A gain calibration device and method for differential push-pull (DPP) tracking error signals in an optical storage system is provided. The gain calibration method processes the synthesized gain (SPPG) of the sub beam in the DPP tracking error signal components with respect to the main beam. The calibration theorem resides in controlling the objective lens of the pick-up head to form a lens-shift or controlling the tilt of the objective lens relative to the optical disc to make the synthesized DPP tracking error signals generate a correspondingly signal variation owing to the optical path deviation. The synthesized gain is calibrated to make the signal variation a minimum value, and the calibrated synthesized gain is the optimum value.

Abstract: A method for defect management of an optical disc. The optical disc includes a plurality of data blocks and a plurality of spare blocks, each data block is for recording data, each spare block is for replacing a defect data block to record a data. The method includes recording a status of the spare blocks in a status table according to a location order of the spare blocks, such that the statuses of neighboring spare blocks with different statuses are recording in neighboring items of the status table.

Abstract: A differential switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of eliminating clock feedthrough and preventing an unwanted momentary frequency shift and drift in the VCO output frequency when the switched capacitor circuit is shut off. A center switch element connects a positive side capacitance node with a negative side capacitance node depending on a first control signal. A positive side primary switch element and a negative side primary switch element connect the positive and negative side capacitance nodes depending on the first control signal. A positive side additional switch element and negative side additional switch element with control signals complementary to the first control signal cancel the clock feedthrough of the center switch and the positive and negative side primary switch elements at the positive and negative side capacitance nodes respectively.

Abstract: A sampling clock generator for BCA data decoding providing a sampling clock, which is proportional to the actual rotation speed of a disk. The sampling clock generator includes a frequency counter, a divider and a frequency divider. The frequency counter counts the number of pulses of a reference clock for each period of a rotation speed indicating signal of a spindle motor and generates a counting value. The divider divides the counting value by a predefined value and generates a divided value. The frequency divider is employed to generate the sampling clock. The frequency divider receives the reference clock and divides the frequency of the reference clock by the divided value to generate the sampling clock. The frequency divider also adjusts the phase of the sampling clock according to the BCA reproducing signal.

Abstract: The invention provides a decoding circuit and a decoding method of a Viterbi decoder. The decoding circuit of the Viterbi decoder includes a branch metric unit, an add-compare-select unit and a path memory unit. The path memory unit includes a data string controller, a trace write-in register array, an idling register array and a decoding register array. In this invention, a run length limited code is used for effectively solving the problem of generating a complicated trellis diagram after the trellis diagram of the Viterbi decoder is subjected to a longitudinal arrangement. In addition, the register array can perform other operations at different times. Accordingly, a high decoding speed of the Viterbi decoder can be achieved without requiring a lot of registers for data processing.

Abstract: An ATIP (absolute time in pre-groove) bit data generator free from an uneven duty cycle. The ATIP bit data generator includes an analog processor, a high-frequency clock generator, a first decoder, a sync pattern detector, and a second decoder. The analog processor receives a signal generated from an optical pickup, and further processes the signal to generate an ATIP FM signal. The high-frequency clock generator provides a high-frequency clock using the ATIP FM signal as a reference signal. The first decoder receives the ATIP FM signal and the high-frequency clock and generates bi-phase data. The sync pattern detector receives the bi-phase data and the high-frequency clock, and generates a sync indication signal. The second decoder counts the pulse number of the high-frequency clock for each counting cycle, and the counting cycle includes a plurality of half periods of the ATIP FM signal.

Abstract: An apparatus for power controlling in a transmitter for detecting the output power without using a power coupler includes a plurality of stage amplifiers, a plurality of matching circuits, at least one power detector, and a bias control circuit. The stage amplifiers receive an emission signal and amplify the power thereof. The matching circuits are connected between the stage amplifiers for matching with the stage amplifiers, respectively. The power detector detects the power of the stage amplifiers and generates detection signals, respectively. The bias control circuit receives the detection signals of the power detector, thereby generating a bias of each of the stage amplifiers in order to optimize the efficiency of each of the stage amplifiers according to the magnitude of the power of each of the stage amplifiers.

Abstract: An apparatus and a method for forming a data structure that improves error resilience when applied to the coding of hierarchical subband decomposed coefficients, e.g., wavelet transform coefficients. The texture unit is defined as comprising only those AC transform coefficients that are located in one or more slices in a single subband. The texture unit is defined as comprising only those AC transform coefficients that are across “n” subbands, where “n” is smaller number than the total number of “N” levels of decomposition. A texture unit can also be defined as comprising only those bits from the DC transform coefficients that form a single bitplane.

Abstract: An error correction code generator uses an additional static random access memory (SRAM) or a multi-symbol encoder to improve the encoding efficiency. During the encoding operation, the number of the data access of the dynamic random access memory (DRAM) with the row address switching can be reduced considerably via using the additional SRAM or multi-symbol encoder. Hence, the efficiency of the data access of the DRAM is improved and the encoding time of the error correction code generator is reduced.

Abstract: A circuit in an optical read/write device for protecting synchronizing patterns is proposed. The protection circuit utilizes a clock with constant frequency as a reference clock. The circuit for protecting synchronizing patterns of this present invention includes a SYNC detector, a frame period counter, a valid-frame-period judgment unit, a frame period memory, a window generator, a real SYNC judgment unit, a SYNC lock judgment unit, and a SYNC signal generator. The circuit counts the pulse number of a reference clock with constant frequency for each frame to get a constant frame period. Then, the circuit can correctly interpolate the lost frame SYNC signal immediately by counting the reference clock, when the disk is defected.

Abstract: A multimode filter in an optical storage device is used for filtering an error signal and outputting a frequency signal. The multimode filter comprises a CLV and CAV mode filter and a switch. The CLV mode filter is used for filtering the error signal and extracting a narrow bandwidth signal, whereas the CAV mode filter is used for filtering the error signal and extracting a wide bandwidth signal. The switch is used for selecting either the CLV mode filter or the CAV mode filter according to the recording mode of the optical storage device.

Abstract: A defect detection method is used to generate a disc defect signal while recording or reproducing information recorded onto an optical disc. The method compares the difference between a reflected light intensity signal (SBAD) and a low-pass filtered SBAD with a predetermined level. A defect signal is generated during a period when the difference exceeds a predetermined value. The defect signal opens a switch to hold the low-passed signal of the SBAD and disconnects the low-pass filter from the SBAD at the moment a defect signal occurs. The held value of the low-passed signal effectively replaces the low-passed signal until the difference between the SBAD and held low-passed signal returns to within the predetermined limits, which re-closes the switch re-connecting the low-pass filter to the SBAD.

Abstract: A method of searching a new writable address (NWA) for an optical recordable medium includes providing an optical pickup head and setting a first search starting point thereof; determining if NWA is located at the latest track and setting a search finishing point of the optical pickup head; setting a second search starting point as the distance between the search finishing point and the first search starting point is less than a first predetermined block time duration; decoding the stored digital information and lasting the step of decoding for a third predetermined block time from the first search starting point; and detecting whether a run-out block has been decoded during a N block time duration, wherein said N block time duration is less than said third predetermined block time duration, and determining said new writable address.

Abstract: A differential charge pump circuit for eliminating influence of mismatches between current sources is disclosed. The differential charge pump circuit includes a floating capacitor for providing an output voltage, a slicer for outputting a comparison signal to control a charge/discharge actions of the floating capacitor, a first current source, a second current source, a first-common-mode current source, a second-common-mode current source, and a third-common-mode current source connected in parallel with the first current source. The differential charge pump circuit of the present invention utilizes switches to switch the charge and discharge current paths of the capacitor with respect to the common mode current source and the charge/discharge current source. Therefore, the duty cycle of the output signal is free from being adversely influenced by the mismatches between the current sources.

Abstract: A method for reading a table of content (TOC) of a multi-session optical medium is provided. This method includes providing a memory for storing the TOCs of sessions having stored said digital information therein, reading TOC stored in the memory out as the change of the digital information state is adding another session, and combining the stored TOCs with the TOC of the newly-added session together, and changing the digital information state of the latest-stored session at first, and then storing the changed digital information state of the latest-stored session into the memory as the change of the digital information state is not adding another session.

Abstract: A method for generating header and transition flags using the DPD technology and an optical device using the same are disclosed. The method first sets a first and a second threshold levels. Then, the method generates a phase difference signal, i.e. starting a phase detection function to generate a phase difference signal. The method generates a first transition flag signal and a second transition flag signal, wherein the first transition flag signal is enable if the phase difference signal is greater than a first threshold level and the second transition flag signal is enable if the phase difference signal is smaller than the second threshold level. The method then generates a first header flag signal and a second header flag signal according to the transition flag signal.

Abstract: An EFM/EFM+ encoding system is adapted to modulate a source symbol sequence into a modulated bit sequence that is further converted to a channel bit sequence, which is to be recorded on a recording medium and which has a cumulative Digital Sum Value (DSV), through NRZI conversion. An apparatus for performing DSV protection in the EFM/EFM+ encoding system includes a DSV calculation unit for calculating the DSV associated with the EFM/EFM+ modulated bit sequence, and a decision unit for adjusting at least a bit in the modulated bit sequence according to the result calculated by the DSV calculation unit such that the channel bit sequence from the NRZI conversion of the adjusted modulated bit sequence accumulates a relatively small DSV. A method of using the EFM/EFM+ encoding system to inhibit disc copying is also disclosed.

Abstract: A computing system includes a digital signal processor, a storage medium for storing parameter tables, a central processing unit coupled to the digital signal processor and the storage medium, and a shared memory coupled to the digital signal processor and the central processing unit. The digital signal processor stores a data request in the shared memory and issues a request command to the central processing unit when access to the parameter tables is desired. Upon receipt of the request command, the central processing unit reads the data request in the shared memory, accesses the storage medium for retrieving requested data that corresponds to the data request, stores the requested data in the shared memory, and issues a response command to the digital signal processor. The digital signal processor retrieves the requested data from the shared memory upon receipt of the response command from the central processing unit.

Abstract: A method of storing an array of digital data, for example, pixel data of a picture in a video bit stream, into a memory. In one embodiment, the memory includes a plurality of memory pages, and each memory page has a first memory section and a second memory section. The method includes a first step of dividing the array of digital data into a plurality of block units, while each of the block units has a plurality of odd rows and a plurality of even rows, and each of the odd rows and the even rows has at least one byte. The method further includes a second step of storing subsequent odd rows of at least one of the block units into consecutive storage locations in the first memory section, and storing subsequent even rows of at least one of the block units into consecutive storage locations in the second memory section. In this way, the memory bandwidth can be used more efficiently.