Abstract: In a method and apparatus for enabling fast clock phase locking in a phase-locked loop, a sampling clock generator generates sampling clock signals in response to an oscillator output of the phase-locked loop. A detector unit samples an input digital signal to the phase-locked loop at clock edges of the sampling clock signals to obtain multiple sampling points of the input digital signal, and compares logic levels of each temporally adjacent pair of the sampling points to detect presence of a logic level transition in the input digital signal. A selector unit is controlled by the detector unit to select one of the sampling clock signals, which has one of the clock edges thereof defining an interval that was detected to have occurrence of the logic level transition in the input digital signal, and which is subsequently provided to the phase-locked loop as an input phase-locking clock signal.

Abstract: A video decoder, a video reproduction apparatus and a method for decoding and displaying an encoded video data are provided. The video reproduction device is capable of decoding the encoded video data and generating reference pictures and non-reference pictures in accordance with a decode order, and displaying the reference pictures and the non-reference pictures in accordance with a display order. The non-reference pictures are not referred to by any other pictures when the video data is encoded.

Abstract: In a method and apparatus for reducing clock jitter in a clock recovery circuit, a control signal having first and second potentials is generated from ascending and descending pulses of a phase detector that receives an input data signal and a clock signal. The current output of a charge controller is used to charge and discharge a capacitor when the control signal has the first potential such that the capacitor has a floating voltage. The capacitor is connected to a loop filter to enable the latter to generate a control voltage corresponding to the floating voltage when the control signal has the second potential. The control voltage is used to control an oscillator circuit for synchronizing the clock signal with the input data signal.

Abstract: A method and device are provided for jitter enhancement in an optical disc system. The optical disc system generates a signal that includes an effective component having a first slew rate, and a pre-pit component having a second slew rate larger than the first slew rate. The signal is fed to a slew rate control module having a predetermined slew rate that is larger than the first slew rate and smaller than the second slew rate. The slew rate control module outputs a component of the signal having a slew rate not larger than the predetermined slew rate, and suppresses a component of the information signal having a slew rate larger than the predetermined slew rate.

Abstract: Apparatus and method of power compensation and optical device using the same. The power compensation apparatus is used to compensate a write power of the optical device. The power compensation apparatus has a signal extraction circuit, a gain setting unit, and an adder. The signal extraction circuit is used to extract a absolute value of a portion of a servo error signal over a threshold voltage. The gain setting unit is used to generate a compensation signal using a gain thereof to adjust the absolute value of the portion of the servo error signal over the threshold voltage. The adder is used to add the compensation signal into the write power.

Abstract: The invention provides a phase lock loop (PLL) in a controller of an optical disk system and methods therefor. According to a preferred embodiment of the invention, the PLL comprises a write phase detector, a read phase detector, and a common read/write module shared by the write and read phase detectors. Further according to the invention, the common read/write module comprises a read/write mode selector coupled to the write and read phase detectors, a charge pump coupled to the mode selector, a loop filter coupled to the charge pump, and a voltage control oscillator (VCO) coupled to the loop filter.

Abstract: In method and apparatus for calibrating laser write power for writing data onto an optical storage medium, test data is written onto a test area of the optical storage medium at a number (N) of laser power levels. The test data written onto the test area is read and processed so as to generate a number (N) of processed signals corresponding to the number (N) of laser power levels, respectively. A jitter value associated with each of the processed signals is determined. Finally, one of the laser power levels that corresponds to one of the processed signals having the jitter value that is at a relative minimum is selected. The laser write power is set to the selected one of the laser power levels.

Abstract: In a method of measuring group delay (Tgd) of a device under test, an analog input signal having a predetermined period (T) is provided to the device under test so as to obtain a delayed output signal from the device under test. A phase difference is detected between first and second digital signals converted from the analog input signal and the delayed output signal, respectively. A current (I) corresponding to the phase difference flows through a circuit having a predetermined resistance (R) so as to result in a potential difference (&Dgr;V). As such, the group delay (Tgd) of the device under test is determined as a function of the predetermined period (T), the current (I), the predetermined resistance (R), and the potential difference (&Dgr;V). An apparatus for measuring the group delay (Tgd) of the device under test is also disclosed.

Abstract: An optical recording system includes a laser light source that provides an incident recording light signal for recording information on an optical recording medium, an optical detector for detecting a reflected write pulse from the optical recording medium, and a light source controller for controlling recording laser beam power of the laser light source according to a mark formation effectiveness signal generated by a signal generating device. The signal generating device includes an analog peak value detector for detecting a peak value of the reflected write pulse from the optical detector, at least one sample-hold circuit for sampling the reflected write pulse to obtain at least one amplitude value, and a processor for generating the mark formation effectiveness signal according to the peak value and the amplitude value.

Abstract: In a method and apparatus for reducing data dependent phase jitter in a clock recovery circuit, a time delay component is connected between the phase detector and the charge controller to cause consecutive ones of ascending and descending pulses from a phase detector to overlap in the time domain. The time delay component cooperates with the phase detector to simultaneously provide the overlapping ascending and descending pulses to a charge controller such that ripples in a control voltage generated by a loop filter and attributed to a current output of the charge controller can be reduced in order to minimize phase jitter of a clock signal from an oscillator circuit.

Abstract: An EFM/EFM+ encoding system is adapted to modulate a source symbol sequence into a modulated bit sequence that is further converted to a channel bit sequence, which is to be recorded on a recording medium and which has a cumulative Digital Sum Value (DSV), through NRZI conversion. An apparatus for performing DSV protection in the EFM/EFM+ encoding system includes a DSV calculation unit for calculating the DSV associated with the EFM/EFM+ modulated bit sequence, and a decision unit for adjusting at least a bit in the modulated bit sequence according to the result calculated by the DSV calculation unit such that the channel bit sequence from the NRZI conversion of the adjusted modulated bit sequence accumulates a relatively small DSV. A method of using the EFM/EFM+ encoding system to inhibit disc copying is also disclosed.

Abstract: A circuit and method for protecting the minimum run length in RLL code is disclosed. The circuit comprises three state processors, each having a plurality of registers, including a decision bit, an invalid bit, metric bits and path bit array, and changing state at the zero crossing point (Turning) of an RF signal, before the zero crossing point (Before) and after the zero crossing point (After). A metric computing unit is used to calculate the metrics at the points of turning, before and after corresponding to the EFM (Eight-Fourteen Modulation) signal. A timing unit is used to generate control signals to the state processors and metric computing unit according to the EFM signal. Then the protecting circuit comprises a computing unit to control the decision bit, the invalid bit, the metric bits and path bit array and generates correct output signals according to the control signals and the metrics.

Abstract: A circuit and method for protecting the run length in RLL (run length limited) code is proposed to correct the illegal run length in an EFM (eight to fourteen modulation) signal. The proposed circuit comprises a sampling unit for sampling a RF signal with a high frequency sampling clock, and generating a high frequency sampling signal. The frequency of the high frequency sampling clock is higher then the frequency of the EFM signal. A detector is employed to receive and to detect the high frequency sampling signal whether there is any illegal run length in the EFM signal, and to generate control signals. Two reference signal generators are employed to generate an ideal front reference signal and an ideal rear reference signal, respectively, corresponding to the control signals. A first difference generator and a second difference generator are employed to generate a first difference and a second difference according to the front and rear reference signals and the high frequency sampling signal, respectively.

Abstract: An optical disk drive includes an optical pickup unit, a tracking coil motor and a sled motor that drive movement of the optical pickup unit, and a servo control system. The optical pickup generates a tracking error signal indicative of amount of shift of the optical pickup unit relative to a track position of an optical disk, and a central error signal indicative of amount of shift of the optical pickup unit relative to an optical path. The servo control system generates a tracking coil control signal based on the tracking error signal for controlling operation of the tracking coil motor to adjust the optical pickup unit relative to the track position of the optical disk, and generates a sled motor control signal based on the central error signal for controlling operation of the sled motor to adjust the optical pickup unit relative to the optical path.

Abstract: In a method and apparatus for processing a microphone audio signal, the microphone audio signal is converted into an initial digital signal at a first sampling frequency. The initial digital signal is stored in a memory at a second sampling frequency lower than the first sampling frequency. The initial digital signal stored in the memory is processed so as to result in a processed digital signal. The processed digital signal is outputted at an output frequency equal to the first sampling frequency. The initial digital signal and the processed digital signal are combined to result in a composite digital signal. Finally, the composite digital signal is converted into an analog processed audio signal output.

Abstract: A memory address generator includes a write address generator for generating write addresses to be used in writing of data units of an input data block into a memory device in a non-raster scan arrangement, a read address generator for generating read addresses to be used in reading of the data units of the input data block from the memory device in a raster scan arrangement, and a scan pattern analyzer for enabling the read address generator after enabling the write address generator such that an optimum number of the write addresses for the writing of the input data block has been generated prior to generation of the read addresses for the reading of the input data block in order to ensure that the reading of each of the data units from the memory device can lag the writing of each of the data units into the memory device.

Abstract: In a method and apparatus for controlling the power of a laser beam in an optical recording system that includes a laser light source, an optical detector detects a reflected write pulse that is a reflection of an incident recording light signal from the optical recording medium, and a signal generating device generates a mark formation effectiveness (MFE) signal according to the reflected write pulse. A laser power compensation circuit includes a filter for filtering the MFE signal so as to result in a first component, and a combiner for combining the first component and the MFE signal so as to result in a second component. The laser power compensation circuit controls laser beam power of the laser light source according to the first and second components for optimum information recording.

Abstract: In a method of controlling multiple decoders in an optical disc player system to read encoded bitstream data divided into multiple sectors from a buffer memory, one of the sectors stored in the buffer memory is read according to a reading pointer associated with one of the decoders that sent out a bitstream request. When a header portion of the sector that is being read from the buffer memory indicates a bitstream type corresponding to that of the bitstream request, a data portion of the sector is transferred to the decoder that sent out the bitstream request, and the reading pointer is adjusted to point to a next one of the sectors stored in the buffer memory. An optical disc player system for implementing the method is also disclosed.

Abstract: Simplified DVD-Audio decoders and encoders are provided. The decoder does not include FIFOs between the depacketizer and the decoder cores. Rather, the decoder cores directly receive data from the depacketizer. Underflow is avoided by spinning the DVD at a speed higher than the nominal, single speed of the DVD, which ensures that data are available at a sufficient rate. Similarly, an encoder provides data directly from an encoding core into a packetizer, eliminating the FIFOs from the data path.

Abstract: In a phase-locked loop frequency synthesizer, a first variable frequency divider is connected between a reference signal generator and a first controllable synchronous frequency divider. A second frequency divider is connected between a second controllable synchronous frequency divider and a voltage controlled oscillator. A phase-frequency comparator compares first and second low frequency signals from the first and second controllable synchronous frequency dividers and outputs an adjust signal according to a detected difference therebetween. A phase-locked detector outputs a phase-locked signal in response to the adjust signal. A switching control logic is operable so as to supply a frequency dividing control signal to the first and second controllable synchronous frequency dividers with reference to a divided reference signal from the first variable frequency divider upon receiving the phase-locked signal from the phase-locked detector.