Abstract: A semiconductor device includes a substrate; a first terminal and a second terminal; and a conductor arranged on the substrate between the first terminal and the second terminal to constitute an inductor shaped for forming a first loop and a second loop arranged side-by-side along a first direction. A crossing of the conductor with itself is present between the first loop and the second loop. The first loop and the second loop define a first enclosed area and a second enclosed area, respectively. At least one ground bar traverses either the first loop or the second loop.

Abstract: A semiconductor package includes a partitioned package substrate that is composed of multiple discrete substrates arranged in a side-by-side manner. The discrete substrates include a central substrate and peripheral substrates surrounding the central substrate. At least one integrated circuit die is mounted on a first surface of the partitioned package substrate. A plurality of solder balls is mounted on a second surface of the partitioned package substrate opposite to the first surface.

Abstract: A video device, a wireless audio device and a method for performing audio and video (AV) synchronization between the video device and the wireless audio device are provided. The method includes: utilizing a controller of the video device to determine a video delay of the video device; utilizing the controller to determine an audio delay of the video device; utilizing the controller to receive information of a communications quality of the wireless audio device from the wireless audio device, to determine a wireless communications delay between the video device and the wireless audio device according to the communications quality; utilizing the controller to generate a time map information according to the video delay, the audio delay and the wireless communications delay; and transmitting the time map information from the video device to the wireless audio device for AV synchronization between the video device and the wireless audio device.

Abstract: A wireless communication device includes a network interface circuit and a control circuit. The network interface circuit communicates with a first wireless communication device and a second wireless communication device, where there is a peer-to-peer link established between the first wireless communication device and the second wireless communication device. The control circuit generates a first frame, and sends the first frame to the second wireless communication device through the network interface circuit, where the first frame is arranged to inform the second wireless communication device of a subband transition at the first wireless communication device.

Abstract: A compute-in-memory (CIM) circuit includes a processing circuit. The processing circuit includes a data-selection circuit and a charge-domain passive summation circuit. The data-selection circuit includes a memory array and a selection circuit. The memory array stores a plurality of candidate weights. The selection circuit selects a target weight from the plurality of candidate weights stored in the memory array. The charge-domain passive summation circuit generates an analog computation result of an input received by the processing circuit and the target weight stored in the memory array through a weighted capacitor array integrated with the memory array.

Abstract: A semiconductor device includes an electronic device, a guard trace and a first trace. The guard trace is connecting to a ground layer through a first ground via. The first trace is disposed adjacent to the electronic device and the guard trace and includes a first segment. A phase or a direction of a first current signal conducted on the first trace is changed in the first segment. The electronic device and the first trace are disposed at different sides of the guard trace and the first ground via is beside the first segment.

Abstract: A digital-to-analog converter (DAC) includes a plurality of DAC cells, a mismatch error sorting circuit, and a dynamic element matching (DEM) circuit. The mismatch error sorting circuit generates a sorting result of the plurality of DAC cells according to mismatch error levels of the plurality of DAC cells. The DEM circuit shapes the mismatch error levels of the plurality of DAC cells according to the sorting result of the plurality of DAC cells.

Abstract: A capacitor weighted segmentation buffer includes a push-pull buffer circuit and a plurality of capacitors. The capacitors include a first capacitor having a first terminal coupled to a control terminal of the first transistor and a second terminal arranged to receive a first input signal; a second capacitor having a first terminal coupled to a control terminal of the second transistor and a second terminal arranged to receive the first input signal; a third capacitor having a first terminal coupled to the control terminal of the first transistor and a second terminal arranged to receive a second input signal; and a fourth capacitor having a first terminal coupled to the control terminal of the second transistor and a second terminal arranged to receive the second input signal.

Abstract: Aspects of the disclosure provide a method to activate secondary cell group (SCG) selectively. For example, the method can include receiving a radio resource control (RRC) reconfiguration message including first and second radio resource configurations of first and second primary secondary cells (PSCells) and conditional PSCell addition (CPA) and conditional PSCell change (CPC) triggering conditions, setting a current triggering condition to be the CPA triggering condition, evaluating the current triggering condition and determining that the first PSCell satisfies the current triggering condition, and performing a CPA step to add the first PSCell as a current SCG, updating the current triggering condition to be the CPC triggering condition, the UE still keeping the first and second radio resource configurations and the CPA and CPC triggering conditions for subsequent CPC step, without releasing the second radio resource configuration and the CPA and CPC triggering conditions associated with the second PSCell.

Abstract: A correlation computation method includes: performing, by a grouping circuit, a grouping operation upon a data sequence according to an in-phase code sequence and a quadrature code sequence, wherein the data sequence is derived from a quadrature phase shift keying (QPSK) modulated signal; performing at least one accumulation operation upon data samples categorized into at least one data sample group by the grouping operation, to generate at least one accumulation result; and deriving a correlation value between the data sequence and both of the in-phase code sequence and the quadrature code sequence from the at least one accumulation result.

Abstract: Aspects of the disclosure provide methods and apparatuses for wireless communication. In some embodiments, a first mobile device can receive a first indication of a first transmit activity pattern associated with a second mobile device that transmits data to the first mobile device via a radio interface without passing through a base station. The first mobile device can compute a first receive activity pattern that is inclusive of at least the first transmit activity pattern. The first mobile device monitors the radio interface according to the first receive activity pattern.

Abstract: A wireless communication includes a control circuit and a receiver (RX) circuit. The control circuit obtains indicator information from another wireless communication system, identifies a transmitter (TX) and receiver (RX) packet delivery scenario as one of a packet overlapping scenario and a packet non-overlapping scenario according to the indicator information, and generates RX gain control information in response to the TX and RX packet delivery scenario. The RX circuit refers to the RX gain control information to set an RX gain used for receiving data.

Abstract: A semiconductor package includes a package substrate; a semiconductor die mounted on a top surface of the package substrate; a plurality of conductive elements disposed on a bottom surface of the package substrate; and a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements. The land-side silicon capacitor includes at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region.

Abstract: A method for processing instant application messages is provided. The method is performed by a device and includes: receiving, by a modem of the device, an instant application message transmitted from an application server to an application processor of the device; determining, by the modem, whether the application processor is in a sleeping mode and the instant application message is an emergency message; and transmitting, by the modem, the instant application message to a co-processor of the device to cache the instant application message when the application processor is in the sleeping mode and the instant application message is not an emergency message.

Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.

Abstract: Various schemes pertaining to encoding and transmit power control for downsized trigger-based (TB) physical-layer protocol data unit (PPDU) transmissions in next-generation WLAN systems are described. A station (STA) receives a trigger frame indicating an allocated resource unit (RU) of a first size. The STA performs channel sensing responsive to receiving the trigger frame. In response to detecting at least one subchannel being busy from the channel sensing, the STA performs a downsized trigger-based (TB) transmission with a downsized RU or multi-RU (MRU) of a second size smaller than the first size by utilizing downsized RU or MRU allocation information while maintaining a value of each of one or more parameters unchanged in an encoding process to perform the downsized TB transmission.

Abstract: A first apparatus communicates with a second apparatus via a first link in a first frequency band and via a second link in a second frequency band different than the first frequency band by performing operations. For example, the first apparatus performs an independent enhanced distributed channel access (EDCA) on each of the first link and the second link. Then, the first apparatus obtains a transmit opportunity (TXOP). Next, the first apparatus synchronizes a starting time and/or an ending time of a transmission and a reception on the first link and the second link to avoid causing an in-device coexistence (IDC) interference due to the transmission and the reception occurring simultaneously. Alternatively, the first apparatus refrains from transmitting and receiving on the first link and the second link simultaneously to avoid causing the IDC interference.

Abstract: An arbitrary-scale blind super resolution model has two designs. First, learn dual degradation representations where the implicit and explicit representations of degradation are sequentially extracted from the input low resolution image. Second, process both upsampling and downsampling at the same time, where the implicit and explicit degradation representations are utilized respectively, in order to enable cycle-consistency and train the arbitrary-scale blind super resolution model.

Abstract: A crystal oscillator (XO) and a method for performing startup of the XO are provided. The XO includes a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit includes a resistive circuit. The frequency detection circuit generates a detection voltage according to a driving signal associated with an auxiliary signal generated by the auxiliary oscillator and a first impedance of the resistive circuit. During a first powered on phase, the auxiliary oscillator is calibrated by utilizing the XO core circuit as a reference after startup of the XO core circuit is completed, and the resistive circuit is calibrated according to the detection voltage. During a second powered on phase, a frequency of the driving signal is calibrated according to the detection voltage, and the driving signal is injected to the XO core circuit for accelerating the startup of the XO core circuit.

Abstract: A method for generating a high resolution image from a low resolution image includes retrieving a plurality of low resolution image patches from the low resolution image, performing discrete wavelet transform on each low resolution image patch to generate a first image patch with a high frequency on a horizontal axis and a high frequency on a vertical axis, a second image patch with a high frequency on the horizontal axis and a low frequency on the vertical axis, and a third image patch with a low frequency on the horizontal axis and a high frequency on the vertical axis, inputting the three image patches to a dual branch degradation extractor to generate a blur representation and a noise representation, and performing contrastive learning on the blur representation and the noise representation by reducing a blur loss and a noise loss.