Abstract: A method of extremely high coding rates for next-generation wireless local area network (WLAN) systems involves coding an input data at a first coding rate using codes designed for coding up to a second coding rate lower than the first coding rate to provide a coded data. The method also involves wirelessly transmitting the coded data.

Abstract: A mainboard, display device, displaying method, and computer readable storage medium are provided. The mainboard has at least two display interfaces, a detecting circuit, and a processor. The at least two display interfaces are used for connecting to different displays. The detecting circuit is coupled to the at least two display interfaces, for detecting the electrical signal of the display. The processor is coupled to the detecting circuit, for determining information about the display connected to the display interface based on the electrical signal detected by the detecting circuit.

Abstract: A push-pull power amplifier (PA) includes a pair of P-type transistors, a pair of N-type transistors, and a splitter, wherein source terminals of the pair of P-type transistors are coupled to a first reference voltage, source terminals of the pair of N-type transistors are coupled to a second reference voltage, and drain terminals of the pair of P-type transistors and drain terminals of the pair of N-type transistors are coupled to an output port of the push-pull PA. The splitter is arranged to receive a common-mode input pair, and provide two differential output pairs to the pair of P-type transistors and the pair of N-type transistors, wherein one of the two differential output pairs is provided to gate terminals of the pair of P-type transistors, and the other of the two differential output pairs is provided to gate terminals of the pair of N-type transistors.

Abstract: A noise filter circuit includes a filter and a transistor off-resistance control circuit. The filter includes a first transistor and a charge storage component. The first transistor has off-resistance when turned off or operated under sub-threshold region. A control terminal of the first transistor is not directly tied to a reference voltage, and is used to receive a first control voltage. The charge storage component has one terminal coupled to a connection terminal of the first transistor. The transistor off-resistance control circuit is coupled to the first transistor, and arranged to set the first control voltage for controlling the off-resistance of the first transistor.

Abstract: The present invention provides a clock buffer, wherein the clock buffer receives an input signal at a first node and generate an output signal at a second node. The clock buffer includes a P-type transistor, a first N-type transistor, a resistor, a transistor and a switch. A source electrode, a gate electrode and a drain electrode of the P-type transistor are coupled to a supply voltage, the first node, and the second node, respectively. A gate electrode, a drain electrode and a source electrode of the first N-type transistor are coupled to the first node, the second node and a third node, respectively. The resistor is coupled between the first node and the second node. The transistor is coupled between the first N-type transistor and a ground voltage. The switch is configured to selectively connect the third node to the ground voltage.

Abstract: A reconfigurable crystal oscillator and a method for reconfiguring a crystal oscillator are provided. The reconfigurable crystal oscillator includes a transconductance circuit, a feedback resistor, a crystal tank, an input-end capacitor and an output-end capacitor. Both of the feedback resistor and the crystal tank are coupled between an input terminal and an output terminal of the transconductance circuit. The input-end capacitor is coupled to the input terminal of the transconductance circuit, and the output-end capacitor is coupled to the output terminal of the transconductance circuit. In particular, the transconductance circuit is configured to provide a transconductance, and when an operation mode of the reconfigurable crystal oscillator is switched, an input-end capacitance of the input-end capacitor and an output-end capacitance of the output-end capacitor are switched, respectively.

Abstract: The present invention provides a wireless communication method of an electronic device, wherein the wireless communication method includes the steps of: determining one link plan from a plurality link plans; using the determined link plan as a current link plan to configure a first link and a second link of the electronic device; determining whether the current link plan satisfies a first condition; in response to the current link plan satisfying the first condition, determining whether performance of another link plan is better than performance of the current link plan; and in response to the performance of another link plan being better than the performance of the current link plan, determining the another as the current link plan to configure the first link and the second link of the electronic device to communicate with the another electronic device.

Abstract: Methods of data handling for one or more protocol layers in a node of a communications system are described. For example, the methods comprise a first set of functions using destination information of a packet and a second set of functions using flow identifier information of a packet, and encompass routing the packet to one or more peer nodes according to an indicated destination of the packet.

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

Abstract: Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

Abstract: A one-coil multi-core inductor-capacitor (LC) oscillator is provided. The one-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer wire and a central wire, wherein the outer wire is coupled to a first core circuit and a second core circuit, and the central wire is coupled between a first node and a second node of the outer wire. More particularly, an outer loop formed by the outer wire corresponds to a first mode of the one-coil multi-core LC oscillator, and inner loops formed by the outer wire and the central wire correspond to a second mode of the one-coil multi-core LC oscillator, where the at least one mode suppression device is configured to suppress one of the first mode and the second mode.

Abstract: Video encoding methods and apparatuses include receiving reconstructed video samples, determining an initial clipping setting for ALF coefficients, deriving clipping setting candidates from the initial clipping setting. ALF coefficients for the initial clipping setting and the clipping setting candidates are derived by solving inverse matrices, where partial intermediate results of solving ALF coefficients are shared by two or more clipping settings. A distortion value corresponds to the derived ALF coefficients for each clipping setting is computed, and final clipping indices for final ALF coefficients are determined according to the distortion values. ALF filtering is applied to the reconstructed video samples based on the final ALF coefficients and the final clipping indices.

Abstract: A method for 3D gesture interaction across electronic devices includes: measuring spatial location information of the electronic devices based on Location Technology; generating a 3D gesture field of the electronic devices based on the spatial location information; setting the location update method, the detection method of 3D gesture, the frequency band of detecting 3D gesture, and the time sequence of detecting gesture at different devices; detecting the cooperative gesture; generating interactive auxiliary messages based on the detection of the cooperative gesture; updating the 3D gesture field if the location of any devices have update; identifying the cooperative gesture in the 3D gesture field of the electronic devices; performing the commands corresponding to the cooperative gesture; detecting that the cooperative gesture is beyond the 3D gesture field of the electronic devices; and sending the cooperative gesture to other electronic devices based on the direction of the cooperative gesture.

Abstract: A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.

Abstract: A correlation computation method includes: obtaining a plurality of code sequences; performing, by a transformation circuit, a bit-wise combination with transformation upon the plurality of code sequences to generate a composite code sequence; and generating a correlation value between a data sequence and the composite code sequence.

Abstract: A method for adjusting a transmitting (TX) power ratio of a radio module includes: separating multiple radio modules into multiple radio groups according to a radiofrequency (RF) regulation, wherein the multiple radio modules comprise the radio module; mapping an RF exposure limit to a TX power limit; interacting with at least one other radio module for adjusting the TX power ratio, to obtain at least one adjusted TX power ratio, wherein the radio module and the at least one other radio module are comprised in a same radio group of the multiple radio groups; and adjusting the TX power limit according to the at least one adjusted TX power ratio, to generate an adjusted TX power limit of the radio module.

Abstract: A semiconductor die includes an on-die power switch and a target device. The on-die power switch includes a plurality of power input nodes, a power output node, and a switch circuit. The power input nodes receive a plurality of operation voltages from a plurality of different power sources, respectively. The power output node outputs a target operation voltage selected from the operation voltages. The switch circuit selectively couples one of the power input nodes to the power output node. The target device operates according to the target operation voltage supplied from the on-die power switch. The on-die power switch and the target device are separate circuit blocks of the semiconductor die.

Abstract: A wafer level chip scale package includes a bare silicon die having an active surface, a rear surface opposite to the active surface, and a sidewall surface between the active surface and the rear surface. The bare silicon die includes a backside corner between the rear surface and the sidewall surface. A plurality of pads is disposed on the active surface. A plurality of conductive elements is disposed on the plurality of pads, respectively. A backside tape is adhered to the rear surface by using an adhesive layer. The adhesive layer and the backside tape protrude beyond the sidewall surfaces of the bare silicon die. The adhesive layer extends along the sidewall surface and wraps around the backside corner.

Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.

Abstract: An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.