Abstract: A vertical interconnection structure of a multi-layer substrate includes a first via pad disposed in a first layer of metal interconnect of the multi-layer substrate; a second via pad disposed in a second layer of metal interconnect of the multi-layer substrate; a signal via electrically connecting the first via pad to the second via pad; a non-circular first ground plane disposed in the first layer of metal interconnect of the multi-layer substrate and surrounding the first via pad; and a non-circular first ground pullback region between the first via pad and the non-circular first ground plane for electrically isolating the first via pad from the non-circular first ground plane.
Abstract: An audio device is provided. The audio device includes processing circuitry which is connected to a loudspeaker and a microphone. The processing circuitry is configured to play an echo reference signal from a far end on the loudspeaker, and perform an acoustic echo cancellation (AEC) process using the echo reference signal and an acoustic signal received by the microphone using an AEC adaptive filter. The processing circuitry repeatedly determines a first status of the loudspeaker according to a relation between the played echo reference signal and the received acoustic signal, and transmits a first status signal indicating the first status of the loudspeaker to the far end through a cloud network.
Type:
Grant
Filed:
November 1, 2021
Date of Patent:
January 2, 2024
Assignee:
MEDIATEK INC.
Inventors:
Shaw-Min Lei, Yiou-Wen Cheng, Liang-Che Sun
Abstract: A headset with ambient sound aware function may include at least one microphone (MIC), a storage device, and a processing circuit. The at least one MIC may be arranged to pick up an ambient sound. The storage device may be arranged to store at least one predetermined sound class. The processing circuit may be arranged to receive the ambient sound sent by the at least one MIC, and analyze the ambient sound to detect whether the ambient sound belongs to the at least one predetermined sound class.
Abstract: A method for scheduling reception activity of a communication apparatus to receive wireless signals from a network device in a wireless network, comprising: collecting information regarding network and operation of the communication apparatus; determining a scenario of the communication apparatus according to the information regarding network and operation of the communication apparatus; determining one or more reception related parameters according to the scenario of the communication apparatus; and scheduling one or more reception activities in at least one Discontinuous Reception (DRX) off duration according to the one or more reception related parameters.
Type:
Application
Filed:
August 23, 2022
Publication date:
December 28, 2023
Applicant:
MediaTek Singapore Pte. Ltd.
Inventors:
Yanyan Qi, Fei Xu, Jianwei Zhang, Mingjun Xu, Yaochao Liu, Nien-En Wu, Jun Hu
Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.
Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.
Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.
Abstract: A method executed by a relay UE is provided. The relay UE establishes a first Radio Link Control (RLC) channel between a first remote UE and the relay UE, in which the first RLC channel is associated with a first end-to-end identifier. The relay UE establishes a second RLC channel between a second remote UE and the relay UE, in which the second RLC channel is associated with the first end-to-end identifier or a second end-to-end identifier. The relay UE receives an incoming SideLink (SL) transmission from the first remote UE on the first RLC channel, in which the incoming SL transmission includes the first end-to-end identifier. The relay UE sends an outgoing SL transmission to the second remote UE on the second RLC channel, in which the outgoing SL transmission includes one of the first end-to-end identifier and the second end-to-end identifier.
Type:
Grant
Filed:
February 26, 2021
Date of Patent:
December 26, 2023
Assignee:
MEDIATEK SINGAPORE PTE. LTD.
Inventors:
Nathan Edward Tenny, Guan-Yu Lin, Xuelong Wang, Ming-Yuan Cheng
Abstract: A semiconductor device includes a semiconductor die having an active surface, an opposite surface, a vertical sidewall extending between the active surface and the opposite surface, and input/output (I/O) connections disposed on the active surface. A redistribution layer (RDL) is disposed on the active surface of the semiconductor die. A plurality of first connecting elements is disposed on the RDL. A molding compound encapsulates the opposite surface and the vertical sidewall of the semiconductor die. The molding compound also covers the RDL and surrounds the plurality of first connecting elements. An interconnect substrate is mounted on the plurality of first connecting elements and on the molding compound.
Abstract: Video encoding methods and apparatuses in a video encoding system receive an input residual signal of a current block by a shared transform circuit, apply horizontal transform and vertical transform by a shared transform circuit to generate transform coefficients, apply quantization and inverse quantization to generate recovered transform coefficients, apply inverse vertical transform and inverse horizontal transform to the recovered transform coefficients by the shared transform circuit to generate a reconstructed residual signal for the current block, and encode the current block based on quantized levels of the current block. The shared transform circuit and a coefficient buffer in the folded 4-time transform architecture reuse computation resources in each transform stage. In some embodiments of the folded 4-time transform architecture, a hierarchical design for block size grouping is implemented with fixed throughput for uniform hardware scheduling.
Abstract: A tri-level digital-to-analog converter (DAC) element includes a first DAC cell. The first DAC cell includes a first reference circuit, a second reference circuit, and a switch circuit. The first reference circuit provides a first reference signal. The second reference circuit provides a second reference signal. The first switch circuit receives a control input from an input port of the tri-level DAC element, and controls interconnection between the first reference circuit, the second reference circuit, and an output port of the tri-level DAC element according to the control input. During a period in which the tri-level DAC element operates in a “0” state, the first switch circuit is arranged to couple at least one of the first reference circuit and the second reference circuit to the output port of the tri-level DAC element.
Abstract: A method for performing channel usage management with aid of multi-link operation architecture and associated apparatus are provided. The method applicable to a wireless transceiver device within a wireless communications system may include: utilizing the wireless transceiver device to communicate with another device within the wireless communications system through at least one portion of multiple links respectively corresponding to multiple predetermined radio frequency bands; and at first time point when radar is detected in a first channel used by a first link among the multiple links, starting performing a first procedure to make channel management information be received by the other device via one or more other links among the multiple links at any time point when the other device is ready to receive the channel management information, wherein the other device is not ready to receive the channel management information at the first time point.
Abstract: A gain equalizer and a method for controlling a tunable gain of the gain equalizer are provided. The gain equalizer includes a common source stage and a switch array. The common source stage is configured to apply the tunable gain to an input signal, in order to generate an amplified signal. The common source stage includes input transistors and cascode transistors, wherein the cascode transistors are respectively coupled to the input transistors. The input transistors are configured to receive the input signal via gate terminals of the input transistors, respectively, and the cascode transistors are configured to output the amplified signal via drain terminals of the cascode transistors, respectively. In addition, the switch array is coupled between respective source terminals of the cascode transistors, wherein the tunable gain is controlled according to an equivalent impedance of the switch array.
Abstract: Techniques for compensating high-speed digital-to-analog converters (DACs) for static mismatch are described. In ideal circumstances, the current sources of a DAC are identical to each other, leading to a frequency response presenting a relatively flat noise spectrum. In the presence of mismatch, however, the response creates unwanted spurious content, which can negatively affect the DAC's dynamic range. The techniques described herein involve randomized thermometric encoders. First, the direction in which a packet contracts or expands, depending on the value to be encoded, can be randomized. Second, pairs of values in a packet (and/or pairs of values outside the packet) can be swapped with one another in a randomized fashion. Third, the decision of whether to apply randomization or not can itself be randomized. By applying one or more of the randomization techniques described herein, the negative effects of switch timing offset and errors in DC linearity can be mitigated.
Abstract: A joint pilot detection method includes: obtaining a plurality of input signals that are derived from a plurality of satellite signals transmitted from a plurality of global navigation satellite system (GNSS) satellites, respectively, wherein each of the plurality of satellite signals carries a pilot component modulated by a secondary code; obtaining a plurality of code sequences that are replicas of secondary codes of the plurality of satellites, respectively; performing a plurality of correlation operations according to the plurality of input signals and the plurality of code sequences, for generating a plurality of correlation results, respectively; and performing pilot detection by jointly considering the plurality of correlation results.
Abstract: The present invention provides a device including a first power delivery channel and a second power delivery channel. The first power delivery channel includes a first voltage regulator, wherein the first voltage regulator is configured to receive a first input voltage to generate a first output signal. The second power delivery channel includes a second voltage regulator and a third voltage regulator, wherein the second voltage regulator receives a second input voltage to generate a second output signal, and the third voltage regulator receives the second output signal to generate a converted second output signal, wherein the first output signal and the converted second output signal are coupled together to a core circuit.
Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, a molding compound disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the molding compound. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.
Abstract: An amplifier circuit includes a voltage-to-current conversion circuit and a current-to-voltage conversion circuit. The voltage-to-current conversion circuit generates a current signal according to an input voltage signal, and includes an operational transconductance amplifier (OTA) used to output the current signal at an output port of the OTA. The current-to-voltage conversion circuit generates an output voltage signal according to the current signal, and includes a linear amplifier (LA), wherein an input port of the LA is coupled to the output port of the OTA, and the output voltage signal is derived from an output signal at an output port of the LA.
Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE detects one or more signals transmitted from a base station in a first unit of a set of units contained in a bandwidth part of an unlicensed carrier, the first unit having contiguous frequency resources. The one or more signals indicating that the base station has occupied the first unit for a first time duration and indicating a schedule of a set of slots in the first time duration for communication with the base station. The UE receives, in a first time slot of the set of slots and from the base station, a control channel.
Abstract: A multi-path voltage-controlled oscillator (VCO) includes a VCO core circuit and a control voltage generator circuit. The VCO core circuit includes a varactor that has a control node for receiving a control voltage. The control voltage generator circuit receives at least one proportional path (P-path) control input and an integral path (I-path) control input, and generates and outputs the control voltage to the control node of the varactor according to the at least one P-path control input and the I-path control input.
Type:
Application
Filed:
May 31, 2023
Publication date:
December 14, 2023
Applicant:
MEDIATEK INC.
Inventors:
Tsz-Bin Liu, Mohammed Mohsen Abdulsalam Abdullatif, Ahmed Safwat Mohamed Aboelenein Elmallah, Mohammed Tamer Ali