Patents Assigned to Mega Chips Corporation
  • Patent number: 9082205
    Abstract: Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: July 14, 2015
    Assignee: MEGA CHIPS CORPORATION
    Inventor: Gen Sasaki
  • Patent number: 9082206
    Abstract: Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: July 14, 2015
    Assignee: MEGA CHIPS CORPORATION
    Inventor: Gen Sasaki
  • Patent number: 8531546
    Abstract: Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: September 10, 2013
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Publication number: 20120002080
    Abstract: Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption.
    Type: Application
    Filed: September 12, 2011
    Publication date: January 5, 2012
    Applicant: MEGA CHIPS CORPORATION
    Inventor: Gen Sasaki
  • Patent number: 8035652
    Abstract: OSD data YD includes a color designating signal As and a color changing signal Ex. When a color register number is designated by the color designating signal As, a color storage unit 41 outputs an appropriate color signal. A Y signal is branched from the outputted color signal and subjected to a modulating process by the color changing signal Ex. The Y changing signal obtained by the modulating process is merged with a Cb signal and a Cr signal so as to form new color signal. The OSD data YD with changed color is subjected to a synthesizing process with image data XD according to the predetermined mixture ratio.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: October 11, 2011
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Patent number: 8023010
    Abstract: First pixel data of a pixel of interest is output from a first shift register, while second and third pixel data of neighboring pixels indicative of the same color are output from second and third shift registers, respectively. Differential data between estimated pixel data calculated from the second and third pixel data and the first pixel data is input to a comparator. A threshold value stored in a register is modulated by the estimated pixel data, and is input to the comparator as modulated threshold data. When the comparator judges that the differential data is greater than the modulated threshold data, a selector outputs the estimated pixel data as corrected pixel data.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: September 20, 2011
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Publication number: 20110150350
    Abstract: It is an object to provide a method of calculating a coding cost by which the magnitude relation of the amounts of generated codes can be estimated with high accuracy. A cost calculation part generates a differential block between a coding object block and a prediction block. Hadamard Transform is performed on the differential block to generate a frequency component block. A conversion factor matrix is generated with the information of a quantization matrix reflected thereon. A coding cost is calculated by multiplying components in the frequency component block individually by components in the conversion factor matrix and adding up the multiplied components. A mode selection part selects an optimum predictive coding method on the basis of the coding cost.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 23, 2011
    Applicant: MEGA CHIPS CORPORATION
    Inventors: Makoto SAITOH, Yuki Haraguchi
  • Patent number: 7911514
    Abstract: First pixel data of a pixel of interest is output from a first shift register, while second and third pixel data of neighboring pixels indicative of the same color are output from second and third shift registers, respectively. Differential data between estimated pixel data calculated from the second and third pixel data and the first pixel data is input to a comparator. A threshold value stored in a register is modulated by the estimated pixel data, and is input to the comparator as modulated threshold data. When the comparator judges that the differential data is greater than the modulated threshold data, a selector outputs the estimated pixel data as corrected pixel data.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: March 22, 2011
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Patent number: 7812866
    Abstract: First pixel data of a pixel of interest is output from a first shift register, while second and third pixel data of neighboring pixels indicative of the same color are output from second and third shift registers, respectively. Differential data between estimated pixel data calculated from the second and third pixel data and the first pixel data is input to a comparator. A threshold value stored in a register is modulated by the estimated pixel data, and is input to the comparator as modulated threshold data. When the comparator judges that the differential data is greater than the modulated threshold data, a selector outputs the estimated pixel data as corrected pixel data.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: October 12, 2010
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Patent number: 7777791
    Abstract: First pixel data of a pixel of interest is output from a first shift register, while second and third pixel data of neighboring pixels indicative of the same color are output from second and third shift registers, respectively. Differential data between estimated pixel data calculated from the second and third pixel data and the first pixel data is input to a comparator. A threshold value stored in a register is modulated by the estimated pixel data, and is input to the comparator as modulated threshold data. When the comparator judges that the differential data is greater than the modulated threshold data, a selector outputs the estimated pixel data as corrected pixel data.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: August 17, 2010
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Patent number: 7598985
    Abstract: In image input devices such as digital still cameras, processing is speeded up and power consumption is reduced by arranging in a RPU (23) performing real time processing of a pixel data from a CCD (21), such that only special exceptional image processing not being prepared previously is subjected to a software program processing in a CPU (24) and, in post processing in which a general image processing is carried out, a pixel data temporarily stored in a main memory (29) is inputted again to the RPU (23) and then processed. This enables to sharply speed up processing, and minimize a prolonged processing in the CPU (24) to reduce power consumption, when compared to the case of executing by software problem processing.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: October 6, 2009
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Publication number: 20090245683
    Abstract: First pixel data of a pixel of interest is output from a first shift register, while second and third pixel data of neighboring pixels indicative of the same color are output from second and third shift registers, respectively. Differential data between estimated pixel data calculated from the second and third pixel data and the first pixel data is input to a comparator. A threshold value stored in a register is modulated by the estimated pixel data, and is input to the comparator as modulated threshold data. When the comparator judges that the differential data is greater than the modulated threshold data, a selector outputs the estimated pixel data as corrected pixel data.
    Type: Application
    Filed: June 9, 2009
    Publication date: October 1, 2009
    Applicant: MEGA CHIPS CORPORATION
    Inventor: Gen SASAKI
  • Publication number: 20090009370
    Abstract: A transcoder calculates a reference conversion factor on the basis of a ratio between a total target bit rate of a whole second stream and an total input bit rate of a whole first stream and calculates a coefficient of variation from the total target bit rate of the whole second stream and an average output bit rate of a converted second stream in the N period. Next, a quantization step conversion factor in the next (N+1) period is calculated by adding the coefficient of variation to the reference conversion factor. Then, a quantization step value of a second stream in the (N+1) period is calculated by multiplying a quantization step value of a first stream in the (N+1) period by the quantization step conversion factor.
    Type: Application
    Filed: June 23, 2008
    Publication date: January 8, 2009
    Applicants: MEGA CHIPS CORPORATION, NTT ELECTRONICS CORPORATION
    Inventors: Hiromu Hasegawa, Miyuki Yanagida
  • Patent number: 7457014
    Abstract: An SPU (image processor) includes: a plurality of defective pixel correction circuits each for correcting a color component signal associated with a defective pixel of an image sensor in accordance with a control signal; an input control circuit for receiving defect correction data transferred from a memory at a time of input of a plurality of color component signals; and a timing generator for generating the control signal based on the defect correction data. The defective pixel correction circuits correct color component signals associated with one and the same defective pixel in parallel, at the same time in accordance with the control signal.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: November 25, 2008
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Patent number: 7408587
    Abstract: An image conversion device is provided with a first buffer area for storing either one of even field and odd field of inputted dot sequential data and a second buffer area for storing the other thereof. A data transfer control circuit controls in such a manner that, during a period in which one of the two fields is written in the first buffer area, the other field, stored in the second buffer area, is read out in a color field sequential format, and during a period in which the other field is written in the second buffer area, the other field, stored in the first buffer area, is read out in a color field sequential format. A pixel interpolating circuit carries out an insertion-interpolating process on the field read out from the image storing unit, and outputs the resulting data. Thus, it becomes possible to prevent color breaking at the time of displaying motion images on a color field sequential type display by using a buffer area having a capacity of one frame.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: August 5, 2008
    Assignee: Mega Chips Corporation
    Inventors: Takashi Matsutani, Gen Sasaki
  • Publication number: 20080030600
    Abstract: First pixel data of a pixel of interest is output from a first shift register, while second and third pixel data of neighboring pixels indicative of the same color are output from second and third shift registers, respectively. Differential data between estimated pixel data calculated from the second and third pixel data and the first pixel data is input to a comparator. A threshold value stored in a register is modulated by the estimated pixel data, and is input to the comparator as modulated threshold data. When the comparator judges that the differential data is greater than the modulated threshold data, a selector outputs the estimated pixel data as corrected pixel data.
    Type: Application
    Filed: June 20, 2007
    Publication date: February 7, 2008
    Applicant: MEGA CHIPS CORPORATION
    Inventor: Gen Sasaki
  • Publication number: 20080030602
    Abstract: OSD data YD includes a color designating signal As and a color changing signal Ex. When a color register number is designated by the color designating signal As, a color storage unit 41 outputs an appropriate color signal. A Y signal is branched from the outputted color signal and subjected to a modulating process by the color changing signal Ex. The Y changing signal obtained by the modulating process is merged with a Cb signal and a Cr signal so as to form new color signal. The OSD data YD with changed color is subjected to a synthesizing process with image data XD according to the predetermined mixture ratio.
    Type: Application
    Filed: October 5, 2007
    Publication date: February 7, 2008
    Applicant: MEGA CHIPS CORPORATION
    Inventor: Gen SASAKI
  • Publication number: 20070280539
    Abstract: The present invention relates to an interpolation method and a filtering method which utilize a correlation between pixel signals, and it is an object of the present invention to provide a sharp and high-quality image even if an error occurs in correlation degree judgment. To accomplish the above-mentioned object, an imaging device 10 is of a single-chip type, and includes a RGB Bayer pattern color filter 11, and an image is processed in a manner to be described below. Pixel signals outputted from the imaging device 10 are inputted through a signal processing part 20 to an image processing part 30. A correlation judgment part 31 judges a correlation between the pixel signals, and an interpolation processing part 32 performs a pixel interpolation process based on a correlation result. Thus, each pixel signal becomes a perfect signal having all R, G and B color components.
    Type: Application
    Filed: October 4, 2005
    Publication date: December 6, 2007
    Applicant: Mega Chips Corporation
    Inventors: Hiromu Hasegawa, Yusuke Nara
  • Publication number: 20070242144
    Abstract: First pixel data of a pixel of interest is output from a first shift register, while second and third pixel data of neighboring pixels indicative of the same color are output from second and third shift registers, respectively. Differential data between estimated pixel data calculated from the second and third pixel data and the first pixel data is input to a comparator. A threshold value stored in a register is modulated by the estimated pixel data, and is input to the comparator as modulated threshold data. When the comparator judges that the differential data is greater than the modulated threshold data, a selector outputs the estimated pixel data as corrected pixel data.
    Type: Application
    Filed: June 20, 2007
    Publication date: October 18, 2007
    Applicant: MEGA CHIPS CORPORATION
    Inventor: Gen SASAKI
  • Patent number: 7256826
    Abstract: In image input devices such as digital still cameras, processing is speeded up and power consumption is reduced by arranging in a RPU (23) performing real time processing of a pixel data from a CCD (21), such that only special exceptional image processing not being prepared previously is subjected to a software program processing in a CPU (24) and, in post processing in which a general image processing is carried out, a pixel data temporarily stored in a main memory (29) is inputted again to the RPU (23) and then processed. This enables to sharply speed up processing, and minimize a prolonged processing in the CPU (24) to reduce power consumption, when compared to the case of executing by software problem processing.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: August 14, 2007
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki