Abstract: In image input devices such as digital still cameras, processing is speeded up and power consumption is reduced by arranging in a RPU (23) performing real time processing of a pixel data from a CCD (21), such that only special exceptional image processing not being prepared previously is subjected to a software program processing in a CPU (24) and, in post processing in which a general image processing is carried out, a pixel data temporarily stored in a main memory (29) is inputted again to the RPU (23) and then processed. This enables to sharply speed up processing, and minimize a prolonged processing in the CPU (24) to reduce power consumption, when compared to the case of executing by software problem processing.

Abstract: A memory control circuit includes a controller (1A) for controlling a RAM (13) conforming to the standard where source voltage is 2.5 V (SSTL2 standard), and a nonvolatile memory (14) conforming to the standard where source voltage is 3.3 V (LVTTL standard) via a control bus (10) and data buses (11, 12). The control bus (10) for transmitting an address signal and a control signal is shared by these memories (13, 14). The controller (1A) converts internal signals to signals conforming to the standard where source voltage is 2.5 V and outputs the converted signals to the control bus (10). The data buses (11, 12) are provided for the respective memories (13, 14) independently. The number of signal lines can be reduced, and it is possible to prevent signals at high voltage level outputted from the nonvolatile memory (14) from being applied to the RAM (13) driven at low voltages, to cause an occurrence of malfunction at the RAM (13).

Abstract: An object of the present invention is to reduce bit depth and word number of a LUT memory 12 as small as possible, while obtaining &ggr; conversion output data with accuracy superior to the bit depth. Outputting table output data Dout0 and Dout1 which are associated with first table input data RA0 addressed and inputted to the LUT memory 12 and second table input data RA1 obtained by adding “1” thereto, and interpolating them outside the LUT memory 12, thereby obtaining output data having a larger bit depth than the LUT memory 12. At this time, the speed of signal processing is improved by employing a dual port memory as the LUT memory 12 or using a register group for the single port memory. Also, when the second table input data RA1 overflows, a specific value is employed as an alternative.

Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.

Abstract: In order to provide a noise removal method for removing noise signals mixed into an image signal without deteriorating picture quality of the overall image, such zigzag noise signals that the difference between the output levels of two pixels adjacent to each other along a noise generation direction alternately takes positive and negative vales at least three times are detected from noise signals mixed into an image signal. Then, a specific pixel is noted among a plurality of pixels corresponding to the noise signals, for calculating a mean value of the output levels of the noise signals with reference to the specific pixel and correcting the output level of a noise signal corresponding to the said specific pixel with the said mean value.

Abstract: OSD data YD includes a color designating signal As and a color changing signal Ex. When a color register number is designated by the color designating signal As, a color storage unit 41 outputs an appropriate color signal. A Y signal is branched from the outputted color signal and subjected to a modulating process by the color changing signal Ex. The Y changing signal obtained by the modulating process is merged with a Cb signal and a Cr signal so as to form new color signal. The OSD data YD with changed color is subjected to a synthesizing process with image data XD according to the predetermined mixture ratio.

Abstract: It is an object of the present invention to prevent an image distortion from occurring by using a line memory of small memory capacity. For example, an image is decomposed into strip regions 12, and each strip region 12 is filtered together with certain excess data 14 from a neighboring strip region 12 to prevent an image distortion from occurring at the boundary between the strip regions 12 while executing band decomposition on the strip region 12 which is smaller in size than the entire image with a smaller line memory. In the band decomposition, a line memory which supports band decomposition of, for example, 3 decomposition levels is repeatedly and recursively used, whereby band decomposition of deeper decomposition levels is executed without any problems. In this manner, line-based wavelet transform for deeper decomposition levels is executed with a small line memory. Also reverse wavelet transform is executed in the similar manner.

Abstract: The present invention provides an AF evaluation value calculating device in which speed of AF control does not deteriorate even when a number of AF areas are set. The AF evaluation value calculating device for calculating an AF evaluation value used for AF (auto-focus) control of a digital camera, includes: at least one AF evaluation value calculating unit 13 for calculating an AF evaluation value in each of a plurality of AF areas which are set in an image area of image data supplied; and a data transmitter (17a and ch0) for transmitting the AF evaluation value calculated by the AF evaluation value calculator 13 into a predetermined memory by DMA (Direct Memory Access).

Abstract: A hybrid pixel interpolating apparatus (1) has a function of converting raw image data (D1) having one color component for each pixel into pixel interpolated data in which each pixel has a plurality of color components. This hybrid pixel interpolating apparatus (1) includes: a register (2) for holding pixel data in a predetermined pixel region in the raw image data (D1) to be inputted; a plurality of pixel interpolating parts (41, 42, . . . , 4n−1, 4n (n: integer not less than 2)) for sampling pixel data (D2) inputted from the register (2) to execute a pixel interpolating process; and a mixing coefficient calculating part (3) for calculating mixing coefficients (&agr;1, &agr;2, . . . , &agr;n), and also includes a mixing part (5) for fetching and mixing interpolated data (DI1, DI2, . . . , DIn) outputted from the respective pixel interpolating parts (41 to 4n) to output the resultant.

Abstract: An object of the present invention is to reduce bit depth and word number of a LUT memory 12 as small as possible, while obtaining &ggr; conversion output data with accuracy superior to the bit depth. Outputting table output data Dout0 and Dout1 which are associated with first table input data RA0 addressed and inputted to the LUT memory 12 and second table input data RA1 obtained by adding “1” thereto, and interpolating them outside the LUT memory 12, thereby obtaining output data having a larger bit depth than the LUT memory 12. At this time, the speed of signal processing is improved by employing a dual port memory as the LUT memory 12 or using a register group for the single port memory. Also, when the second table input data RA1 overflows, a specific value is employed as an alternative.

Abstract: A noise elimination method of the present invention includes the steps of: detecting a zigzag signal in which a differential value between signal levels of two pixels which are adjacent to each other along a horizontal pixel direction or a vertical pixel direction alternately takes a positive value and a negative value (ST2); determining whether or not the zigzag signal forms a stripe pattern (ST3); regarding the zigzag signal as a normal image signal when the zigzag signal is determined as forming a stripe pattern (ST4); regarding the zigzag signal as a noise signal and extracting the same when the zigzag signal is determined as not forming a stripe pattern (ST5); and filtering this noise signal (ST6).

Abstract: A memory control circuit includes a controller (1A) for controlling a RAM (13) conforming to the standard where source voltage is 2.5 V (SSTL2 standard), and a nonvolatile memory (14) conforming to the standard where source voltage is 3.3 V (LVTTL standard) via a control bus (10) and data buses (11, 12). The control bus (10) for transmitting an address signal and a control signal is shared by these memories (13, 14). The controller (1A) converts internal signals to signals conforming to the standard where source voltage is 2.5 V and outputs the converted signals to the control bus (10). The data buses (11, 12) are provided for the respective memories (13, 14) independently. The number of signal lines can be reduced, and it is possible to prevent signals at high voltage level outputted from the nonvolatile memory (14) from being applied to the RAM (13) driven at low voltages, to cause an occurrence of malfunction at the RAM (13).

Abstract: [Purpose] To reduce a focusing time.

Abstract: An image conversion device is provided with a first buffer area for storing either one of even field and odd field of inputted dot sequential data and a second buffer area for storing the other thereof. A data transfer control circuit controls in such a manner that, during a period in which one of the two fields is written in the first buffer area, the other field, stored in the second buffer area, is read out in a color field sequential format, and during a period in which the other field is written in the second buffer area, the other field, stored in the first buffer area, is read out in a color field sequential format. A pixel interpolating circuit carries out an insertion-interpolating process on the field read out from the image storing unit, and outputs the resulting data. Thus, it becomes possible to prevent color breaking at the time of displaying motion images on a color field sequential type display by using a buffer area having a capacity of one frame.

Abstract: To enable a brightness histogram operation without requiring a special-purpose integration circuit and memory.

Abstract: A game cassette unit which can be connected to a game machine having a CPU for execution of a game selected by a user, including a memory which rewritably stores a plurality of game machine programs and a game selection program that allows a user to select a desired one of these programs. The memory further rewritably stores decode data defining address conversion rules for executing respective of the programs. A decode part executes address conversion based on decode data corresponding to the game selection program after start of power. After the user selects one of the game machine programs, the decode part executes address conversion based on the decode data corresponding to a selected game machine program. Thus, the user can select a desired one from the plurality of game machine programs. As a result, game software is provided to the user at low cost.

Abstract: Image dividing means of an RPU divides raw image data into divided image data A1 having 2048 horizontal pixels and A2 having 1024 horizontal pixels. The divided image data A1 is continuously processed in single pixel processing means and multiple pixel processing means and thereafter transferred to and stored in a buffer. The divided image data A2 is processed in the single pixel processing means and thereafter transferred to and temporarily stored in another buffer. The multiple pixel processing means reads and processes divided image data A2a stored in this buffer and thereafter transfers and stores the same to and in still another buffer. Image combining means reads divided image data A1b and A2b stored in the buffers and combines the same with each other. Thus, an image processing time and a cost can be reduced even if raw image data having horizontal pixels in a number exceeding the capacity of a line memory is received.

Abstract: In order to provide a noise removal method for removing noise signals mixed into an image signal without deteriorating picture quality of the overall image, such zigzag noise signals that the difference between the output levels of two pixels adjacent to each other along a noise generation direction alternately takes positive and negative vales at least three times are detected from noise signals mixed into an image signal. Then, a specific pixel is noted among a plurality of pixels corresponding to the noise signals, for calculating a mean value of the output levels of the noise signals with reference to the specific pixel and correcting the output level of a noise signal corresponding to the said specific pixel with the said mean value.

Abstract: A pixel clock is switched to a high speed for reading culled pixel data from a CCD or switched to a low speed for reading all pixels from the CCD when picking up an image of an object, so that a main memory stores a first field initially read from the CCD and an RPU reads the first field from the main memory in synchronization with reading of a subsequent second field for executing a series of image processing in real time. The main memory stores the processed data. A CPU reads the processed data from the main memory, compresses the processed data and thereafter stores the same in a storage medium. Thus provided is an image processing circuit capable of increasing a frame rate for finder display and efficiently executing image processing at a high speed.

Abstract: The present invention relates to a game program rewrite system for supplying data of a game program of a plurality of terminal stations from a host station and writing the data in portable information storage media applied to game execution units in the terminal stations in response to requests, and a program rewrite system suitable for this game program supply system, and aims at enabling construction of a game-on-demand system including a number of terminal stations with no excess of requirement to equipment of a network or the data throughput of the host station. In order to attain the above object, a host station (1) supplies data of a game program to a terminal station (2) online through a communication network. The data of the game program is supplied to the terminal station (2) offline too. The data of the game program preserved in the terminal station (2) is written in a game execution storage medium (20) in response to a request of a user.