Abstract: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

Abstract: A chip assembly includes a semiconductor chip and a wirebonded wire. The semiconductor chip includes a passivation layer over a silicon substrate and over a thin metal structure, a first thick metal layer over the passivation layer and on a contact point of the thin metal structure exposed by an opening in the passivation layer, a polymer layer over the passivation layer and on the first thick metal layer, and a second thick metal layer on the polymer layer and on the first thick metal layer exposed by an opening in the polymer layer. The first thick metal layer includes a copper layer with a thickness between 3 and 25 micrometers. The wirebonded wire is bonded to the second thick metal layer.

Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.

Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.

Abstract: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

Abstract: A copper pillar may be provided on a chip and a first tin-containing layer may be provided over the copper pillar. A second tin-containing layer may be provided on a substrate. The first tin-containing layer may be joined with the second tin-containing layer during a packaging process.

Abstract: A method for fabricating an integrated circuit (IC) chip includes forming a metal trace having a thickness of between 5?m and 27 ?m over a semiconductor substrate, and forming a passivation layer on the metal trace, wherein the passivation layer includes a layer of silicon nitride on the metal trace and a layer of silicon oxide on the layer of silicon nitride, or includes a layer of silicon oxynitride on the metal trace and a layer of silicon oxide on the layer of silicon oxynitride.

Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.

Abstract: A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad and to the substrate, forming a polymer material on the substrate, covering the semiconductor chip and the wire, next forming a lead-free solder ball on the substrate, and then cutting the substrate and polymer material to form a chip package.

Abstract: A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.

Abstract: An integrated circuit module has a common function known good integrated circuit die with selectable functions. The selectable functions are selected during packaging of the known good integrated circuit die. The known good integrated circuit die is mounted to a second level substrate. The second level substrate has wiring connections to the input/output pads of the known good integrated circuit die that select desired input functions and output functions. Further, the wiring connections on the second level substrate provide signal paths to transfer signals to the desired input function and signals from the desired output function, and signals to and from the common functions. Also, the wiring connections form connections between the input/output pads and external circuitry. To select the desired input functions and the desired output functions, appropriate logic states are applied to input/output pads connected to a function selector to configure a functional operation of the integrated circuit module.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A chip package includes a semiconductor chip, a flexible circuit film and a substrate. The substrate has a circuit structure in the substrate. The flexible circuit film is connected to the circuit structure of the substrate through metal joints, an anisotropic conductive film or wireboning wires. The semiconductor chip has fine-pitched metal bumps having a thickness of between 5 and 50 micrometers, and preferably of between 10 and 25 micrometers, and the semiconductor chip is joined with the flexible circuit film by the fine-pitched metal bumps using a chip-on-film (COF) technology or tape-automated-bonding (TAB) technology. A pitch of the neighboring metal bumps is less than 35 micrometers, such as between 10 and 30 micrometers.

Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.