Abstract: An optical device includes a chip, a set of waveguides on the chip and configured to carry first optical signals modulated with data during a data transmission stage, and an alignment waveguide on the chip. The alignment waveguide is configured to receive a second optical signal during an alignment stage that aligns the set of waveguides with a collimator including a set of lenses. The alignment waveguide is configured to output the second optical signal from the chip. The second optical signal output from the chip is indicative of a quality of alignment between the set of waveguides and the collimator.

Abstract: A data modulator for a transmitter includes a multiplexer configured to receive, at a first rate, a first data stream including a plurality of first symbols and a second data stream including a plurality of second symbols. The multiplexer is configured to selectively output, based on a first clock signal, the plurality of first symbols and the plurality of second symbols to form a third data stream that achieves a second rate greater than the first rate for transmission of the third data stream by the transmitter.

Abstract: A network element includes multiple ports and forwarding circuitry. The ports are configured to serve as network interfaces for exchanging packets with a communication network. The forwarding circuitry is configured to receive a multicast packet that is to be forwarded via a plurality of the ports over a plurality of paths through the communication network to a plurality of destinations, to identify a path having a highest latency among the multiple paths over which the multicast packet is to be forwarded, to forward the multicast packet to one or more of the paths other than the identified path, using a normal scheduling process having a first forwarding latency, and to forward the multicast packet to at least the identified path, using an accelerated scheduling process having a second forwarding latency, smaller than the first forwarding latency.

Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.

Abstract: Systems and methods are described that provide for distributively storing and accessing data across multiple hash tables, such that utilization of the hash tables is optimized. In particular, a key associated with a value is split into two or more sub-keys and the sub-keys are inserted into respective hash tables with associated values. For each sub-key except the final sub-key derived from a particular key, the value paired with the sub-key is an identifier that points to the location of the next sub-key and its associated value, which may be stored in the other hash tables. The final sub-key derived from the original key is paired with the value associated with the key, such as an action to be performed. Thus, rather than using a single key (which may be very large) to access or store a particular value, multiple (smaller) sub-keys are used to ultimately access the same value via multiple, smaller hash tables.

Abstract: An optical cable includes a single optical connector configured for insertion into an optical receptacle so as to receive optical signals at a plurality of different wavelengths from the optical receptacle, and multiple electrical connectors, configured for insertion into respective electrical receptacles. Each electrical connector includes a transceiver configured to convert the optical signals into electrical output signals for output to an electrical receptacle. The optical cable further includes a plurality of optical fibers, having respective first ends connected together to the single optical connector so as to receive the optical signals. Each of the optical fibers has a respective second end coupled to a respective one of the electrical connectors. Wavelength selection optics are associated with the optical fibers so that the transceiver in each of the electrical connectors receives the optical signals at a different, respective one of the wavelengths.

Abstract: In one embodiment, a computer network system, includes at least one lower tier of lower switches, at least one upper tier of upper switches, and a middle tier of middle switches connected down-tier to ones of the lower switches and up-tier to ones of the upper switches, one of the middle switches including a clos topology arrangement of leaf and spine switches, the leaf switches being connected via K internal network connections to the spine switches, each leaf switch being connected to each spine switch, the leaf switches being connected via N down-tier network connections to ones of the lower switches and via M up-tier network connections to ones of the upper switches, there being more of the N down-tier network connections than there are of the M up-tier network connections, and there being less of the K internal network connections than there are of the N and M connections.

Abstract: In one embodiment, a network device includes multiple ports to be connected to a packet data network so as to serve as both ingress and egress ports in receiving and forwarding of data packets including unicast and multicast data packets, a memory coupled to the ports and to contain a combined unicast-multicast user-pool storing the received unicast and multicast data packets, and packet processing logic to compute a combined unicast-multicast user-pool free-space based on counting only once at least some of the multicast packets stored once in the combined unicast-multicast user-pool, compute an occupancy of an egress queue by counting a space used by the data packets of the egress queue in the combined unicast-multicast user-pool, apply an admission policy to a received data packet for entry into the egress queue based on at least the computed occupancy of the egress queue and the computed combined unicast-multicast user-pool free-space.

Abstract: A Multi-Chip-Module (MCM) includes an MCM substrate and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate. The DPIC is configured to send data to the DCIC by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced date and durations of the first time periods and the second time periods, are preset.

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

Abstract: A network element includes multiple output ports and circuitry. The multiple output ports are configured to transmit packets over multiple respective network links of a communication network. The circuitry is configured to receive from the communication network, via one or more input ports of the network element, packets that are destined for transmission via the multiple output ports, to monitor multiple data-counts, each data-count corresponding to a respective output port, and is indicative of a respective data volume of the packets forwarded for transmission via the respective output port, to select for a given packet, based on the data-counts, an output port among the multiple output ports, and to forward the given packet for transmission via the selected output port.

Abstract: One embodiment includes a network device including multiple interfaces to serve as ingress ports for receiving network packets from nodes in remote customer-site network(s) via a tunnel in a provider network, and from nodes in a local customer-site network, and egress ports for forwarding at least some of the network packets, and control circuitry to make a decision to drop a network packet to reduce packet duplication in at least one of the nodes, responsively to the network packet being identified as a packet of broadcast, unknown unicast, or multicast traffic, the network packet being subject to decapsulation of an encapsulation header, being assigned to one of the egress ports, and having a header including one of a plurality of virtual local area network identifications, or one of a plurality of source identifications.

Abstract: A network element includes multiple ports and logic. The multiple ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a network. The logic is configured to queue the packets received from the ingress ports, run a packet-dropping process that randomly drops one or more of the queued packets to avoid congestion, while detecting and excluding from the packet-dropping process, at least probabilistically, packets belonging to a predefined packet type, and forward the queued packets, which were not dropped, to the egress ports.

Abstract: Network communication is carried out by sending packets from a source network interface toward a destination network interface, receiving one of the packets in an intermediate switch of the network, determining that the intermediate switch is experiencing network congestion, generating in the intermediate switch a congestion notification packet for the received packet, and transmitting the congestion notification packet from the intermediate switch to the source network interface via the network. The received packet is forwarded from the intermediate switch toward the destination network interface. The source network interface may modify a rate of packet transmission responsively to the congestion notification packet.

Abstract: In one embodiment, a network device, includes ports to serve as ingress ports and egress ports, a memory to store received network packets, a switch fabric, a controller to monitor queues of the egress ports and make a decision to drop at least a network packet of the received network packets, the network packet having a first destination address associated with a first network node, and mirroring circuitry to encapsulate the network packet with an encapsulation header including a second destination address different from the first destination address, and feedback the encapsulated network packet into a processing pipeline of the received network packets within the network device at a point in the processing pipeline that is prior to egress port assignment, wherein the switch fabric is configured to forward the encapsulated network packet to the packet analyzer responsively to the second destination address in the encapsulation header.

Abstract: In one embodiment, a network device, includes at least one network interface port to serve as at least one ingress port for receiving network packets from a network and as at least one egress port for forwarding network packets to the network, a memory, control circuitry configured to monitor respective events in the network device, the respective events having respective event timestamps, and burst estimator logic to track respective rates of occurrence of ones of the events over respective time periods responsively to respective ones of the event timestamps, follow a maximum one of the rates of occurrence, store, in the memory, the maximum rate of occurrence, and find a measure of burstiness of the events responsively to the followed maximum rate of occurrence.

Abstract: One embodiment includes a communication apparatus, including multiple interfaces including at least one egress interface to transmit packets belonging to multiple flows to a network, and control circuitry to queue packets belonging to the flows in respective flow-specific queues for transmission via a given egress interface, and to arbitrate among the flow-specific queues so as to select packets for transmission responsively to dynamically changing priorities that are assigned such that all packets in a first flow-specific queue, which is assigned a highest priority among the queues, are transmitted through the given egress interface until the first flow-specific queue is empty, after which the control circuitry assigns the highest priority to a second flow-specific queue, such that all packets in the second flow-specific queue are transmitted through the given egress interface until the second flow-specific queue is empty, after which the control circuitry assigns the highest priority to another flow-specifi

Abstract: An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.

Abstract: Apparatus including a network element including an input-output port, the input-output port including an input data lane and an output data lane, wherein the input data lane is in wired connection with a network data source external to the network element, the output data lane is in wired connection with a network data destination external to the network element, and the network data source is distinct from the network data destination. Related apparatus and methods are also described.

Abstract: A network element includes ports, a hardware fabric, a packet classifier and control logic. The ports are configured to transmit and receive packets over a network. The fabric is configured to forward the packets between the ports. The packet classifier is configured to receive at least some of the packets and to specify an action to be applied to a packet in accordance with a set of rules. The classifier includes (i) multiple Ternary Content Addressable Memories (TCAMs), each TCAM configured to match the packet to a respective subset of the set of rules and to output a match result, and (ii) circuitry configured to specify the action to be applied to the packet based on match results produced for the packet by the multiple TCAMs, and based on a priority defined among the multiple TCAMs. The control logic is configured to apply the specified action to the packet.