Abstract: A network element includes output ports, a crossbar fabric and a scheduler. The output ports are organized in groups of multiple output ports selectable over predefined time slots in accordance with a cyclic mapping assigned to each group. In each time slot, the crossbar fabric routes to fabric outputs data received from the buffers via fabric inputs, in accordance with a routing plan. The scheduler determines and applies the routing plan for transmitting packets from the buffers to the communication network via the crossbar fabric and output ports. When in a given time slot, a required readout rate from a given buffer exceeds a maximum rate, the scheduler selects a group of the output ports to which the given buffer is routed in that time slot, and modifies the cyclic mapping for that group to reduce the required readout rate from the given buffer in the given time slot.

Abstract: A network element includes multiple ports, a memory, multiple processors and cache-flushing circuitry. The multiple ports are configured to serve as ingress and egress ports for receiving and transmitting packets from and to a network. The memory is configured to store a forwarding table including rules that specify forwarding of the packets from the ingress ports to the egress ports. The multiple processors are configured to process the packets in accordance with the rules. The two or more cache memories are each configured to cache a respective copy of one or more of the rules, for use by the multiple processors. The cache-flushing circuitry is configured to trigger flushing operations of copies of rules in the cache memories in response to changes in the forwarding table, and to reduce a likelihood of simultaneous accesses to the forwarding table for updating multiple cache memories, by de-correlating or diluting the flushing operations.

Abstract: In one embodiment a network device includes multiple interfaces including at least one egress interface, which is configured to transmit packets belonging to multiple flows to a packet data network, control circuitry configured to generate event-reporting data-items, each including flow and event-type information about a packet-related event occurring in the network device, a memory, and aggregation circuitry configured to aggregate data of at least some of the event-reporting data-items into aggregated-event-reporting data-items aggregated according to the flow and event-type information of the at least some event-reporting data-items, store the aggregated-event-reporting data-items in the memory, and forward one aggregated-event-reporting data-item of the aggregated-event-reporting data-items to a collector node, and purge the one aggregated-event-reporting data-item from the memory.

Abstract: A network element includes one or more ports for communicating over a network, a processor and packet processing hardware. The packet processing hardware is configured to transfer packets to and from the ports, and further includes data-transfer circuitry for data transfer with the processor. The processor and the data-transfer circuitry are configured to transfer between one another (i) one or more communication packets for transferal between the ports and the processor and (ii) one or more databases for transferal between the packet processing hardware and the processor, by (i) translating, by the processor, the transferal of both the communication packets and the databases into work elements, and posting the work elements on one or more work queues in a memory of the processor, and (ii) using the data-transfer circuitry, executing the work elements so as to transfer both the communication packets and the databases.

Abstract: A method includes obtaining (i) an operating-temperature profile of a hardware processing sub-unit (HPSU) of a network element as a function of time, and (ii) a dependence of an Equivalent Reliability Time (ERT) of the HPSU on operating temperature. The operating-temperature profile is weighted using the dependence of the ERT on operating temperature, to estimate an effective ERT of the HPSU. An operating condition of the HPSU in the network element is modified, depending on the effective ERT.

Abstract: Communication apparatus includes multiple ports configured to serve as ingress and egress ports, such that the ingress ports receive packets from a packet data network for forwarding to respective egress ports. The ports include an egress port configured for connection to a network interface controller (NIC) serving multiple physical computing units, which have different, respective destination addresses and are connected to the NIC by different, respective communication channels. Control and queuing logic is configured to queue the packets that are received from the packet data network for forwarding to the multiple physical computing units in different, respective queues according to the destination addresses, and to arbitrate among the queues so as to convey the packets from the queues via the same egress port to the NIC, for distribution to the multiple physical computing units over the respective communication channels.

Abstract: A method including receiving at a buffer at least a portion of an incoming frame, holding in the buffer the at least a portion of the frame received at the buffer, keeping in the buffer the at least a portion of the frame held in the buffer after transmission of the incoming frame by transmission circuitry responsive to receiving a signal at the buffer indicating that the at least a portion of a frame held in the buffer should be kept, and clearing from the buffer the at least a portion of a frame held in the buffer responsive to receiving a signal to the buffer indicating that the at least a portion of the frame held in the buffer should be cleared. Related methods and apparatus are also described.

Abstract: An apparatus includes a network interface and a processor. The network interface is configured to communicate with a network that includes a plurality of switches interconnected in a Cartesian topology having a number D of dimensions. The processor is configured to hold, in a memory, a grid representation of the Cartesian topology, the grid representation including grid points associated respectively with the plurality of switches, to traverse the grid points and assign D-dimensional coordinates to the respective switches, and based on the assigned coordinates, to configure at least some of the switches with routing information via the network interface.

Abstract: A method including providing: a switching device including a main mapping unit configured to provide a main mapping which maps virtual addresses to direct addresses; management logic configured to store a connection tracking table stored in memory and configured for storing a plurality of connection mappings each including a virtual-to-direct mapping from a virtual address to a direct address; and a migrated connection table stored in memory and configured for storing a plurality of migrated connection mappings each including a virtual-to-migrated-direct mapping from a virtual address to a migrated direct address.

Abstract: A method including altering the configuration of a system including a processor, firmware storage and a scratchpad from a first configuration in which a first version of firmware enabling a first plurality of system operations is run by the processor, into a second configuration in which a second version of firmware enabling a second plurality of system operations is run by the processor, the altering including: A) re-configuring the system from the first configuration into an intermediate configuration in which the processor continues to run the first version of the firmware, B) while the system is in the intermediate configuration, disallowing at least one of the first plurality of operations, C) re-configuring the system from the intermediate configuration to the second configuration, and D) while the system is in the second configuration, allowing the second plurality of operations. Related apparatus and methods are also provided.

Abstract: A method for communication includes, in a first network switch that is part of a communication network having a topology, detecting a compromised ability to forward a flow of packets originating from a source endpoint to a destination endpoint. In response to detecting the compromised ability, the first network switch identifies, based on the topology, a second network switch that lies on a current route of the flow, and also lies on one or more alternative routes from the source endpoint to the destination endpoint that do not traverse the first network switch. A notification, which is addressed individually to the second network switch and requests the second network switch to reroute the flow, is sent from the first network switch.

Abstract: A network switch includes multiple ports that serve as ingress ports and egress ports for connecting to a communication network, and processing circuitry. The processing circuitry is configured to receive packets via the ingress ports, select one or more of the packets for mirroring, create mirror copies of the selected packets and output the mirror copies for analysis, mark the packets for which mirror copies have been created with mirror-duplicate indications, and forward the packets to the egress ports, including the packets that are marked with the mirror-duplicate indications.

Abstract: A method including providing a network element including an ingress port, an egress port, and a delay equalizer, providing an equalization message generator, receiving, at the ingress port, a plurality of data packets from multiple sources, each data packet having a source indication and a source-provided time stamp, determining, at the ingress port, a received time stamp for at least some of the received data packets, passing the received data packets, the source-provided time stamps, and the received time stamps to the delay equalizer, the delay equalizer computing, for each source, a delay for synchronizing that source with other sources, the equalization message generator receiving an output, for each source, including the delay for that source, from the delay equalizer and producing a delay message instructing each source regarding the delay for that source, and sending, from the egress port, the delay message to each source. Related apparatus is also provided.

Abstract: In one embodiment, a network device includes an interface to receive packets from sources in a network for forwarding to destinations in the network, the sources and destinations being assigned to groups, each packet including a source and destination identifier, a memory configured to store a source-group mapping table that maps source identifiers to source-groups, a destination-group mapping table that maps destination identifiers to destination-groups, and an intergroup access-control list that maps source-destination-group pairs to forwarding rules, and a single IC chip configured, for each packet, to find a source-group for the source identifier in the source-group mapping table, find a destination-group for the destination identifier in the destination-group mapping table, find a forwarding rule for a source-destination pair including the found source and destination-group in the intergroup access-control list, and forward or drop the packet according to the found forwarding rule.

Abstract: A network element includes circuitry and multiple ports. The multiple ports are configured to connect to a communication network. The circuitry is configured to receive multiple packets from the communication network via one or more input ports, and store the received packets in a buffer of the network element, to schedule transmission of the packets stored in the buffer to the communication network via one or more output ports, and in response to a request to provide a snapshot of at least a portion of the buffer, to mirror for transmission, via one or more dedicated ports, only a part of the portion that was received in the network element prior to the request.

Abstract: Communication apparatus includes multiple interfaces configured to be connected to a network so as to receive and transmit data packets having respective packet headers, which can include sub-headers of different, respective types. A memory stores instructions for parsing each type of sub-headers and a transition table, which indicates, for each of the types, a location of the instructions for parsing a subsequent sub-header depending upon the type of the subsequent sub-header. A plurality of predefined types are represented in the transition table by a common alias. Routing logic parses the first sub-header in a packet, reads the type of the second sub-header from the first sub-header, and accesses the transition table using the common alias in place of the type of the first sub-header so as to locate and read the instructions for parsing the second sub-header.

Abstract: Communication apparatus includes multiple interfaces configured to be connected to a network so as to receive and transmit data packets having respective packet headers that includes a basic header record and one or more optional records. Parsing instructions specify one or more types of the optional records and indicate, for each specified type, an offset within an optional record of the specified type. Upon receiving each packet, routing logic parses the basic header record in the packet, parses the one or more optional records so as to identify any optional records of the one or more specified types, extracts header data from the identified optional records at the offset indicated for the specified type, and processes and forwards the data packets via the interfaces to the network in accordance with information parsed from the basic header record and the extracted header data.

Abstract: A network element includes a data structure, a cache memory and circuitry. The data structure is configured to store multiple rules specifying processing of packets received from a communication network. The cache memory is configured to cache multiple rules including a subset of the rules stored in the data structure. Each rule that is cached in the cache memory has a respective cost value corresponding to a cost of retrieving the rule from the data structure. The circuitry is configured to receive one or more packets from the communication network, to process the received packets in accordance with one or more of the rules, by retrieving the rules from the cache memory when available, or from the data structure otherwise, to select a rule to be evicted from the cache memory, based on one or more respective cost values of the rules currently cached, and to evict the selected rule.

Abstract: A network element connects over a network to a network node via a member link of a Multi-Chassis—Link Aggregation Link Group (MC-LAG), and further connects, using inter-peer ports, to peer network elements coupled to the network node via other MC-LAG member links. A processor of the network element is configured to receive from the network first packets destined to the network node, to receive via the inter-peer ports information indicative of second packets received from the network by the peer network elements that are destined to the network node, to select at least some of the first packets for transmission at an egress rate that jointly with egress rates of the peer network elements does not exceed a predefined MC-LAG maximal rate, based on the first packets and the information, and to transmit the selected first packets to the network node at the egress rate.

Abstract: A network box accepts packets from a network in ingress ports of a first tier of leaf switches, adaptively routes the packets from the leaf switches to a second tier of spine switches within the network box, statically routes the packets from the spine switches to designated egress ports of the leaf switches, and transmits the packets from the designated egress ports into the network.