Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.

Abstract: Described herein are techniques to ensure that an action (e.g., a read or a write by a host device) associated with an element of a memory device that stores a value is valid compared to a reference value. The reference value is associated with an actual characteristic of a memory. The element storing the value can be stored in a region of memory that is configured to store metadata. The element can be re-programmed after the memory device is manufactured, and thus, the value stored in the element can be modified by a host device so that it incorrectly or inaccurately reflects a characteristic of the memory. In contrast, the reference value is stored in a separate region of memory and the reference value is a true value.

Abstract: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

Abstract: Memory devices provide a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also provided.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.

Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: A memory device comprises a first plurality of addressable memory locations associated with a first data storage window and a second plurality of addressable memory locations associated with a second data storage window. The memory device includes a controller that receives requests from a host device to identify the first data storage window and the second data storage window. The controller receives requests to assign a first window index value to the first data storage window and to assign a second window index value to the second data storage window. The controller receives memory commands from the host device that indicate the first window index value and at least one address. The controller accesses, based at least on the first window index value, a location associated with the at least one address within the first plurality of addressable memory locations.

Abstract: This disclosure is directed to systems, apparatuses, and methods of storing a data entity using at least two sectors of a memory device based at least in part on context information of the data entity. For example, the context information may differentiate between large sequential operations and small random operations, and may further improve multitasking support. The context information may further improve operations to erase data in the memory device. For example, a method may include storing a data entity using at least two sectors of a memory device, the at least two sectors associated with the same data entity, and maintaining, at a memory controller, context information of the data entity comprising a pointer to at least one of the at least two sectors of the memory device. The method may further include erasing the at least two sectors of the memory device using the context information.

Abstract: The specification and drawings present a new apparatus and method for managing/configuring by the memory module controller storing operational state data for operating the memory module controller into an extended random access memory comprised in a memory module and in a host system memory of a host device during various operational modes/conditions of the memory module and the host system memory. Essentially, the memory module controller operated as a master for the data transfers as described herein. The operational state data typically comprises state information, a logical to physical (L2P) mapping table and register settings.

Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

Abstract: A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.

Abstract: A semiconductor memory device and front-end method of fabricating nickel plated caps over bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. In some examples, the method and device include one or more conductive and insulating layers formed over a substrate, and a plurality of memory cells over the conductive and insulating layers.

Abstract: Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.

Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.

Abstract: Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.

Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.

Abstract: A storage module includes a set of memories. Each of the memories in the set of memories may be divided into a set of portions. A controller is configured to transfer data between the set of memories and a host connected through an interface. A set of channels connects the set of memories to the controller. The controller is also configured to select: a memory from the set of memories, a portion from the set of portions for the selected memory, and/or a channel from the set of channels, e.g., connected to the selected memory, based upon an identification (ID) associated with the data. The ID may be separate from the data and a write address of the data, and the selected memory, the selected portion, and the selected channel may be used to store the data.