Patents Assigned to Memory Technology
  • Patent number: 12381111
    Abstract: A method of wafer bonding includes: forming a first hole in a first insulation layer disposed over a first substrate; performing a first deposition-self-etch process to deposit a first conductive material in the first hole to form a first conductive plug; forming a second hole in a second insulation layer disposed over a second substrate; performing a second deposition-self-etch process to deposit a second conductive material in the second hole to form a second conductive plug; and bonding the first conductive plug with the second conductive plug to form a first grain fusion layer between the first conductive plug and the second conductive plug.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: August 5, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Chao Wang, Youdong Jiang, Yulong Zhang, Zhiyong Suo
  • Patent number: 12373134
    Abstract: The present disclosure relates to fragmentation evaluation in a memory system. In one example, a method for operating a memory controller includes receiving, from a host, a request for a fragmentation level of a file stored in a memory device. The method further includes determining a read performance level of the file based on a logical-to-physical (L2P) address mapping table corresponding to the file without reading the file from the memory device. The method further includes determining the fragmentation level based on the read performance level.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: July 29, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Zhenran Lu
  • Patent number: 12374378
    Abstract: A monitoring circuit includes: a sampling module, configured to sample an initial address to obtain a monitoring address; a counting module, configured to adjust a counting value of a first counter corresponding to the monitoring address and set a predetermined value for the monitoring address, and a magnitude of the set predetermined value is positively correlated with duration for which the monitoring address is stored in the counting module; and a processing module, configured to compare the counting value of the first counter corresponding to each monitoring address with the predetermined value, where if the counting value of the first counter is greater than or equal to the predetermined value, the monitoring address is retained, and if the counting value of the first counter is less than the predetermined value, the monitoring address is released, and the first counter and the predetermined value corresponding to the monitoring address are reset.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: July 29, 2025
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Runfa Zhou, Kyounghan Kwon
  • Patent number: 12369317
    Abstract: A method for forming a 3D memory device is provided. The method comprises forming an array wafer including a core array region, a staircase region, and a periphery region. Forming the array wafer includes forming an alternating dielectric stack on a first substrate, forming a plurality of channel structures in the alternating dielectric stack in the core array region, each channel structure including a functional layer and a channel layer, forming a staircase structure in the staircase region, and forming a plurality of dummy channel structures. The method further comprises bonding a CMOS wafer to the array wafer; and removing the first substrate; removing a portion of functional layer of each channel structure to expose channel layer, and doping the exposed portion of the channel layer.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: July 22, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Kun Zhang
  • Patent number: 12367936
    Abstract: Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bit line and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bit line can include a first bit line segment coupled to the first memory string group and a second bit line segment coupled to the second memory string group. The buffer can be coupled to the memory array by the bit line. The memory array and the buffer can be included in separate first and second dies, respectively, and the first die can be bonded to the second die.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: July 22, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Teng Chen, Yan Wang, Jing Wei, Yang Zhang, Kuriyama Masao
  • Publication number: 20250231690
    Abstract: An operating method for a memory, a memory, and a memory system are provided in the present application. The memory includes at least a plurality of word lines and a plurality of strings, and the plurality of word lines include a target word line, and each word line is coupled to a plurality of strings. Each string includes a plurality of memory cells. In accordance with the operating method provided by the present application, the first verification and the second verification are performed on a plurality of target memory cells with first and second verify voltages during performing a first programming operation on a plurality of target memory cells in target string coupled to the target word line, and the second start program voltage is determined based on at least the second verification result, ensuring the accuracy of the second start program voltage.
    Type: Application
    Filed: April 7, 2025
    Publication date: July 17, 2025
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventor: Weijun Wan
  • Patent number: 12363896
    Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: July 15, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qiang Xu, Zhiliang Xia, Ping Yan, Guangji Li, Zongliang Huo
  • Patent number: 12363898
    Abstract: Aspects of the disclosure provide a semiconductor device including a first die. The first die includes a first stack of layers including a semiconductor layer on a backside of the first die. A second stack of layers is formed that includes gate layers and first insulating layers alternatingly stacked on a face side of the first die. The face side is opposite to the backside. A vertical structure includes a first portion disposed in the first stack of layers and a second portion extending through the second stack of layers. The first portion has a different dimension than the second portion in a direction parallel to a main surface of the first die.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: July 15, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: LinChun Wu, Wenxi Zhou, Zhiliang Xia, ZongLiang Huo
  • Patent number: 12360916
    Abstract: An example memory controller and readable storage medium are disclosed. An example memory system includes: a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller is configured to: determine whether data for the logical block address mapping of a received read command belongs to tables of a first class or tables of a second class, and confirm the heat of the data corresponding to the logical block address of the received read command; determine a level of the amount of drift of a threshold voltage of a memory cell corresponding to the logical block address, according to the heat of the data corresponding to the logical block address of the received read command; determine different read voltages that are correspondingly sent to the memory cell corresponding to the logical block address, according to different levels of the amount of drift.
    Type: Grant
    Filed: September 21, 2023
    Date of Patent: July 15, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Fanya Bi, Xing Wang, Hua Tan, Zhe Sun, Bo Yu, Guangyao Han
  • Patent number: 12360670
    Abstract: A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: July 15, 2025
    Assignee: Memory Technologies LLC
    Inventors: Olli Luukkainen, Kimmo J. Mylly, Jani Hyvonen
  • Patent number: 12360915
    Abstract: In an example operation method of a controller, a mapping relationship of translation from a first physical block address into a first logical block address is written to a first entry according to a write instruction. The first physical block address is a storage address in a memory, and the first logical block address is a storage address recorded in the write instruction. Storage data is written to the first physical block address. A mapping relationship of translation from the first logical block address into the first physical block address is written to a second entry. When a product of first time and second time is greater than or equal to a first value, the second entry is updated into the memory, wherein the first time is theoretical time for refreshing the first entry, and the second time is theoretical time for refreshing the second entry.
    Type: Grant
    Filed: February 14, 2024
    Date of Patent: July 15, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Guangtao Tan, Jiangwei Shi, Shengfei Yu
  • Patent number: 12353727
    Abstract: A storage module includes a set of memories. Each of the memories in the set of memories may be divided into a set of portions. A controller is configured to transfer data between the set of memories and a host connected through an interface. A set of channels connects the set of memories to the controller. The controller is also configured to select: a memory from the set of memories, a portion from the set of portions for the selected memory, and/or a channel from the set of channels, e.g., connected to the selected memory, based upon an identification (ID) associated with the data. The ID may be separate from the data and a write address of the data, and the selected memory, the selected portion, and the selected channel may be used to store the data.
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: July 8, 2025
    Assignee: Memory Technologies LLC
    Inventor: Kimmo Juhani Mylly
  • Patent number: 12356603
    Abstract: A semiconductor structure includes: a transistor structure and a capacitor structure that are arranged along a first direction, where the capacitor structure extends along the first direction; and a wordline staircase structure extending along the first direction, where the wordline staircase structure and the transistor structure are disposed along a second direction intersecting with the first direction. A plane perpendicular to the second direction is used as a reference plane. An orthographic projection of the transistor structure on the reference plane is a first projection. An orthographic projection of the capacitor structure on the reference plane is a second projection. An orthographic projection of the wordline staircase structure on the reference plane is a third projection. The third projection covers the first projection, and the third projection partially overlaps the second projection.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: July 8, 2025
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Kang You
  • Patent number: 12354994
    Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a conductor/insulator stack over a substrate, forming a dielectric layer of a dielectric material including atomic hydrogen over a part of the conductor/insulator stack, and performing a thermal process to release the atomic hydrogen from the dielectric material and diffuse the atomic hydrogen into the conductor/insulator stack.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: July 8, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhiyong Lu, Sheng Peng, Kai Yu, Wenbo Zhang, Yang Zhou, Jing Gao
  • Patent number: 12347787
    Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. A fabrication method includes forming a semiconductor layer over a substrate, forming an opening that extends partially through the semiconductor layer, depositing a first stack layer and a second stack layer that are alternately stacked over a sidewall of the opening and over the semiconductor layer, and filling the opening with a dielectric material to form an alignment mark.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: July 1, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Chuanhai Shan, Zhaosong Li, Zhouyang Lu, Jing Liu, Jing Gao
  • Patent number: 12347684
    Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: July 1, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lu Ming Fan, Zi Qun Hua, Bi Feng Li, Qingchen Cao, Yaobin Feng, Zhiliang Xia, Zongliang Huo
  • Patent number: 12346681
    Abstract: Embodiments of the present disclosure provide a firmware updating method, an apparatus and a data system. The firmware updating method is applied to the first apparatus, the first apparatus contains at least one PCI configuration space for configuring functions for the first apparatus, and the method specifically includes: configuring firmware updating capability in the first PCI configuration space in the at least one PCI configuration space, and updating the first firmware to the first apparatus based on the firmware updating capability.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: July 1, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Peian Han
  • Publication number: 20250212465
    Abstract: A thin film transistor, a memory, and a method of manufacturing a thin film transistor are provided, which relate to a field of semiconductor device technology. The thin film transistor includes a substrate; a gate on a surface of the substrate; an insulation layer covering the gate; a source and a drain; a channel between the insulation layer and the source and the drain, wherein the source and the drain are located on a surface of the channel away from the substrate; and an insulation dielectric layer between the source and the drain, wherein the insulation dielectric layer partially overlaps with the channel in a first direction, wherein the substrate, the gate, the insulation layer, the source and the drain, the channel, and the insulation dielectric layer are stacked in the first direction.
    Type: Application
    Filed: December 19, 2024
    Publication date: June 26, 2025
    Applicants: Beijing Superstring Academy of Memory Technology, INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Gaobo XU, Yunjiao BAO, Gangping YAN, Chuqiao NIU, Yanyu YANG
  • Patent number: 12341515
    Abstract: Provided are a delay-locked loop (DLL), a delay locking method, a clock synchronization circuit, and a memory. The DLL includes: a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal; a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal; a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals.
    Type: Grant
    Filed: August 16, 2023
    Date of Patent: June 24, 2025
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Siman Li, Yoonjoo Eom
  • Publication number: 20250201308
    Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack over a substrate, wherein the alternating dielectric stack includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate. The method also includes forming a channel structure penetrating through the alternating dielectric stack and extending into the substrate, wherein the channel structure includes a channel layer disposed on a sidewall of a memory film. The method further includes removing the substrate and a portion of the memory film that extends into the substrate to expose a portion of the channel layer; and disposing an array common source (ACS) on the exposed portion of the channel layer.
    Type: Application
    Filed: March 5, 2025
    Publication date: June 19, 2025
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Linchun WU, Kun ZHANG, Wenxi ZHOU