Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes sequentially forming a first and a second dielectric stacks on a substrate. The first dielectric stack includes a first and a second dielectric layers alternatingly stacked in a first direction perpendicular to the substrate. The second dielectric stack comprises a third and a fourth dielectric layers stacked in the first direction. The method further includes forming an etch-stop layer on the second dielectric stack and forming a gate line slit (GLS) trench spacer to cover a sidewall of the etch-stop layer. The method further includes replacing the fourth and the second dielectric layers with conductive layers through a GLS opening to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.

Abstract: Aspects of the disclosure provide a memory system. For example, the memory system can include a memory device configured to store data and one or more parity check codes. The memory system can further include a randomizer configured to generate a sequence of pseudo-randomized numbers using a randomizer seed in response to a clock signal according to a predetermined rule. The memory system can further include a codec coupled to the memory device and the randomizer. The codec can be configured to generate the one or more parity check codes according to the pseudo-randomized numbers and the data. The parity check codes are to be written to the memory device when a write operation is performed and to be used to recover at least one of the data stored in the memory device when a read operation is performed and the at least one of the data is incorrect.

Abstract: An address refresh check method includes: setting a row address with a highest repetition rate or with a quantity of repetition times exceeding a predetermined threshold as a seed address, and determining an address type; if the address type is a random address, obtaining an expected refresh address; performing a row hammer refresh operation to obtain an actual refresh address; and comparing the expected refresh address with the actual refresh address to obtain a check result.

Abstract: A method for controlling a memory system is disclosed. For example, the method can include performing an operation on a memory device of the memory system, calculating a remaining payload based on a current total payload and a payload associated with the operation performed on the memory device, and when the remaining payload meets a predefined requirement, measuring a current temperature of the memory device and setting the current total payload associated with the current temperature for the memory device.

Abstract: In a method for fabricating a semiconductor device, a stack of alternating insulating layers and sacrificial layers are formed over a substrate. A staircase having a plurality of steps are formed in the stack. Each of the steps has a tread and a riser and further includes a respective pair of the insulating layer and the sacrificial layer over the insulating layer of the respective step. A dielectric layer is formed along the treads and risers of the steps and is doped with one or a combination of carbon, phosphorous, boron, arsenic, and oxygen. The sacrificial layers are further replaced with a conductive material to form word line layers that are arranged between the insulating layers. A plurality of word line contacts are formed to extend from the word line layers of the plurality of steps, and further extend through the dielectric layer.

Abstract: A failbit counting method includes controlling a counter of a verify failbit count (VFC) circuit to count fail bits in a bit group including one or more verification bits, received at an input of the counter, to obtain a count result in unary format. Each of the one or more verification bits is a fail bit or a pass bit. The count result in unary format is stored in the counter. The method further includes controlling the counter to transcode the count result stored in the counter from unary format to binary format.

Abstract: In one example, a peripheral circuit in a die is configured to: first, receive control commands, and generate indication information according to the control commands, the control commands being used for indicating the die to determine the address of the die, the indication information being used for indicating M dies to share the same enable pin, M being a positive integer greater than or equal to 1; and then, determine the address of the die according to the indication information, and send the address of the die, the address being used for addressing an enable signal provided by the enable pin.

Abstract: A semiconductor device includes a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. Transitions of the clock signal are output in the gated clock signal in response to a clock enable signal having an enable value and are disabled from being output in the gated clock signal in response to the clock enable signal having a disable value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to the disable value in response to a disable control and sets the clock enable signal to the enable value in response to a wakeup control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides the disable control to the first portion during an operation.

Abstract: A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage cells in the storage array; multiple column select signal units that are connected to sensitive amplifiers, the sensitive amplifiers and the multiple bit lines are disposed in one-to-one correspondence; local data buses that are divided into local data buses O and local data buses E, adjacent bit lines are electrically connected to a respective local data bus O and a respective local data bus E, respectively, through a respective sensitive amplifier and a respective column select signal unit; and a first error checking and correcting unit and a second error checking and correcting unit that are configured to check and correct errors of data.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

Abstract: In certain aspects, a memory device includes an array of memory cells and a peripheral circuit coupled to the array of memory cells. At least one of the memory cells is set to one of 2N levels corresponding to a piece of N-bits data, where Nis an integer greater than 1. The peripheral circuit is configured to apply a first program voltage to a word line of the memory cells, perform a first verification of the word line of the memory cells at a last level of the 2N levels after applying the first program voltage, perform a first verify fail count (VFC) based on a result of the first verification and a first VFC criterion, apply a second program voltage greater than the first program voltage to the first word line of the memory cells after performing the first VFC, and perform a second VFC based on the result of the first verification and a second VFC criterion different from the first VFC criterion within a period of applying the second program voltage.

Abstract: The present disclosure is directed to methods and systems for analyzing integrated circuits. The method includes performing a first resistor capacitor (RC) extraction process on a power-receiving circuit and producing a first RC model. The method also includes scanning a netlist of a power distribution network, the power distribution network electrically connected to the power-receiving circuit. The method further includes determining a selection of circuit elements of the power distribution network based on a predetermined criteria. The method further includes performing a second RC extraction process on the selection of circuit elements and producing a second RC model. The method further includes performing a simulation process on the power-receiving circuit and the power distribution network using the first and second RC models.

Abstract: A capacitor device includes: a substrate; an insulation film, disposed on the substrate; at least one capacitor unit cell, being covered by the insulation film on the substrate, the at least one capacitor unit cell having at least one first electrode and at least one second electrode disposed over the first electrode; an exposed conductive layer, disposed on the at least one capacitor unit cell and the insulation film, the exposed conductive layer having a first conductive pad formed on a first side of the exposed conductive layer and a second conductive pad formed on a second side different from the first side; wherein the first conductive pad and the second conductive pad are electrically connected to the at least one first electrodes and the at least one second electrodes of the at least one capacitor unit cell respectively.

Abstract: Disclosed is a memory device comprising: a memory cell array having a plurality of rows of memory cells; a plurality of word lines coupled to the plurality of rows of memory cells respectively; wherein the memory device is configured to perform programming operations on a target memory cell in the plurality of rows of memory cells, wherein during the programming operations: applying a programming voltage to a selected word line corresponding to a row where the target memory cell locates to program the target memory cell to a target programming state; applying a predetermined voltage to the selected word line to reduce voltage changes caused by capacitive coupling between an unselected word line adjacent to the selected word line and the selected word line; and applying a verification voltage to the selected word line to perform verification operations to verify whether a threshold voltage of the target memory cell is larger than a target threshold voltage corresponding to the target programming state based on

Abstract: A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a dielectric stack over a substrate, forming a functional layer and a semiconductor channel through the dielectric stack, forming a conductor/insulator stack based on the dielectric stack, and forming memory cells through the conductor/insulator stack. Each memory cell includes a portion of the functional layer and the semiconductor channel. At least one of the functional layer and the semiconductor channel includes a certain amount of deuterium elements.

Abstract: a memory device includes an array of memory cells. Each memory cell includes a vertical transistor having a semiconductor body vertically extending in a first direction. Each memory cell includes a storage unit coupled to a first end of the semiconductor body and a bit line extending in a second direction perpendicular to the first direction. The bit line is connected to second ends of the semiconductor bodies of a row of the vertical transistors. The bit line includes a semiconductor epitaxial layer extending in the second direction and connected to the second ends of the semiconductor bodies of the row of the vertical transistors at a top surface of the semiconductor epitaxial layer.

Abstract: A method of fabricating a semiconductor device can include providing a substrate, etching the substrate from a first side to form at least one vertical pillar having a first and a second end, forming at least one gate line on a gate dielectric layer formed on sidewalls of the at least one vertical pillar, forming a first p-type region at the first end of the at least one vertical pillar, forming a storage unit connecting the first p-type region, removing a portion of the substrate at a second side opposite to the first side of the substrate to expose the second end of the at least one vertical pillar, forming a second p-type region made of at least p-type SiGe at the second end of the at least one vertical pillar, and forming a bit line in connection with the second p-type region.

Abstract: In an aspect, a memory device comprises a memory configured to store a program code and a processor. The processor is configured to perform a first programming to a first cell of the memory device by incremental step pulse programming (ISPP) with a first step voltage. The processor is further configured to perform a second programming to a second cell of the memory device by ISPP with a second step voltage. The first step voltage is larger than the second step voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage.

Abstract: An operation method of a memory system includes sending, by a controller, a first scanning command to a memory and determining a valley voltage by scanning a plurality of memory cells. The valley voltage is determined according to a count of memory cells corresponding to different threshold voltages in a preset threshold voltage interval, the count of memory cells corresponding to the different threshold voltages being obtained by scanning the plurality of memory cells, the valley voltage being a threshold voltage corresponding to the minimum count of memory cells in the threshold voltage interval. The operation method includes sending, by the controller, a first read command to the memory, the first read command being used for instructing the memory to use the valley voltage as a reference read voltage to read target data. The operation method also includes reading, by the memory, the target data according to the valley voltage.