Patents Assigned to Mentor Graphics Corporation
  • Patent number: 11095474
    Abstract: A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 17, 2021
    Assignee: MENTOR GRAPHICS CORPORATION
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
  • Patent number: 11089540
    Abstract: A communication unit and discoverable unit communicate according to a protocol in which unit addresses are not of a predetermined length. The communication unit sends a discovery request to the discoverable unit. The discoverable unit receives the discovery request and generates a discovery response. The discovery response comprises an address field of length unknown to the communication unit, populated with an address of the discoverable unit. The discovery response also comprises a flag following the address field. The discoverable unit sends the discovery response to the communication unit. The communication unit receives the discovery response and determines the address field length by counting the number of bits prior to the flag.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: August 10, 2021
    Assignee: MENTOR GRAPHICS CORPORATION
    Inventors: Iain Robertson, Callum Stewart
  • Patent number: 11025754
    Abstract: A system for processing messages of a high rate data stream and an apparatus including: a message processor including a plurality of processor sub-modules and configured to read an input data stream, process the input data stream, and to output an output data stream; at least one payload memory storing data related to the input data stream and accessible to the message processor; at least one instruction memory accessible to the message processor and storing computer program instructions configuring the message processor to process the input data stream; and an application processor configured to rewrite the at least one instruction memory.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 1, 2021
    Assignee: MENTOR GRAPHICS CORPORATION
    Inventor: Kari Vierimaa
  • Patent number: 11022647
    Abstract: A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip. The method comprises the debug unit collecting debug data of the peripheral circuit and outputting the debug data in a message stream. The debug unit receives a debug reconfiguration command. The debug unit transmits an indication of the current debug configuration, then reconfigures the current debug configuration to a new debug configuration in accordance with the debug reconfiguration command, then transmits an indication of the new debug configuration. The indication of the current debug configuration and the indication of the new debug configuration are transmitted adjacent to the debug data in the message stream.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 1, 2021
    Assignee: MENTOR GRAPHICS CORPORATION
    Inventors: Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
  • Patent number: 10977400
    Abstract: Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 13, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Xijiang Lin, Mark A. Kassab, Irith Pomeranz
  • Patent number: 10977075
    Abstract: An apparatus comprising: a processing unit configured to execute a plurality of threads; a profiling unit configured to: profile the operation of the processing unit over a time period to generate an activity profile indicating when each of the plurality of threads is executed by the processing unit over the time period; analyse the generated activity profile to determine whether a signature of the processing unit's thread execution for the time period matches a signature indicating a baseline of thread execution for the processing unit; output an alert signal if the signature of the processing unit's thread execution for the time period does not match the signature indicating a baseline of thread execution for the processing unit.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: April 13, 2021
    Assignee: Mentor Graphics Corporation
    Inventor: Gajinder Singh Panesar
  • Patent number: 10963612
    Abstract: A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 30, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Nilanjan Mukherjee, Jedrzej Solecki, Janusz Rajski
  • Patent number: 10955460
    Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: March 23, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
  • Patent number: 10937509
    Abstract: This application discloses a memory device to retain stored data when receiving a voltage supply having at least a retention voltage level. The retention voltage level varies based on a supply voltage and a temperature of an environment around the memory device. A sensitive circuit can adjust the voltage supply received by the memory device based on the supply voltage and the temperature. The sensitive circuit can alter a memory bias supply voltage for the memory device to adjust the voltage supply towards the retention voltage level. The sensitive circuit can include a temperature dependent circuit to generate a bias voltage based on the supply voltage and the temperature, and an adjustment circuit to alter the memory bias supply voltage based on the bias voltage. The adjustment circuit also can include high temperature circuitry to adjust the memory bias supply voltage based on a leakage current from the memory device.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 2, 2021
    Assignee: Mentor Graphics Corporation
    Inventor: Kwan Him Lam
  • Patent number: 10929582
    Abstract: Circuits may be designed using computer aided design tools and may comprise a plurality of different possible variants of individual components. These multi-variant component circuits may be validated to identify potential problems by generating an aggregate parametric model for the multi-variant components and then using the aggregate parametric model in applying tests to different connection networks of the circuit definition.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 23, 2021
    Assignee: Mentor Graphics Corporation
    Inventor: Michael Alam
  • Patent number: 10929590
    Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: February 23, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz
  • Patent number: 10922468
    Abstract: Systems and methods for systems and methods for generating the complete set of IC design layout clips, or any part of the complete set, satisfying usefulness criteria and of a prespecified size. A method includes generating an initial set of integrated circuit (IC) design layout clips as a current set of IC design layout clips. The method includes removing any of IC design layout clips from the current set of IC design layout clips that do not meet the one or more usefulness criteria. The method includes, while a size of the IC design layout clips is less than a desired clip size, generating a new set of IC design layout clips from the current set of IC design layout clips according to every combination of pairs of the design layout clips in the current set of IC design layout clips, and repeating the removing process.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: February 16, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Mohamed-Nabil Sabry, Kareem Madkour, Sherif Ahmed Abdel-Wahab Hammouda
  • Patent number: 10908511
    Abstract: Systems and methods for multi-patterning in layout design data. A method includes receiving a coloring rule by a computer system. The method includes applying the coloring rule to the layout design data to identify a unique uncolored geometric element corresponding to the rule, by the computer system. The method includes, when the applied rule did not identify the unique uncolored geometric element corresponding to the rule, repeat the receiving and applying processes with a different coloring rule. The method includes, when the applied rule did identify the unique uncolored geometric element corresponding to the rule, assigning a patterning color to the unique uncolored geometric element, by the computer system.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: February 2, 2021
    Assignee: Mentor Graphics Corporation
    Inventor: Fedor G. Pikus
  • Patent number: 10896279
    Abstract: A thermal transient response simulation is performed to determine a total thermal resistance value for a structure having a plurality of thermal model elements. A plurality of thermal transient response simulations are also performed for the structure to determine changed total thermal resistance values by varying one of thermal resistance values of the thermal model elements. Thermal resistance values for the thermal model elements are then determined based on the total thermal resistance value and the changed total thermal resistance values. The structure function is divided into portions associated with the thermal model elements based on the thermal resistance values for the thermal model elements.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 19, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Joseph Charles Proulx, Byron Blackmore, Robin Bornoff, Andras Vass-Varnai
  • Patent number: 10895864
    Abstract: Disclosed systems and methods may support fabric-independent multi-patterning. A system may include a coloring constraint access engine and a fabric-independent multi-patterning engine. The coloring constraint access engine may be configured to access a set of coloring constraints to apply to geometric elements of a circuit design without accessing a fabric layer that defines a layout of the geometric elements of the circuit design, the set of coloring constraints applicable to multi-patterning the geometric elements of the circuit design to support manufacture of circuit layers using multiple manufacturing steps (e.g., via complementary lithographic masks). The fabric-independent multi-patterning engine may be configured to perform, independent of the fabric layer, a pattern coloring process according to the set of coloring constraints to determine a color assignment for the geometric elements, respectively.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 19, 2021
    Assignee: Mentor Graphics Corporation
    Inventor: Fedor G. Pikus
  • Patent number: 10889255
    Abstract: A device for electrical energy management of a vehicle system of a motor vehicle includes a power supply for supplying energy to the vehicle system of the motor vehicle. The power supply has a normal operation mode and a stand-by operation mode. A distributing device has voltage levels on the output side for supplying electrical energy to vehicle system components of the vehicle system. A state-monitoring device monitors the electrical energy supply of the power supply and controls the distributing device. A computer device has an operating system device and a volatile computer data memory that is designed to be kept energized even in the stand-by operation mode of the device for energy management, in such a way that the volatile computer data memory does not lose the data stored therein. A method and a motor vehicle corresponding to the device are also provided.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: January 12, 2021
    Assignees: Bayerische Motoren Werke Aktiengesellschaft, Mentor Graphics Corporation
    Inventors: Daniel Franze, Carsten Schmid, Georg Spoerlein, Reiner Striebel
  • Patent number: 10872191
    Abstract: A system may include an image clustering engine and a cluster provision engine. The image clustering image may be configured to access a set of circuit images and cluster the circuit images into different groups via an unsupervised learning process, wherein clustering by the unsupervised learning process is invariant to each invariant property of an invariant property set. A given invariant property in the invariant property set may correspond to a given image transformation, the invariant properties in the invariant property set may be discrete, and the total number of invariant properties in the invariant property set may be finite. The cluster provision engine may be configured to provide the clustered circuit images for further processing or analysis by an electronic design automation (EDA) application.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: December 22, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Fedor G. Pikus, Muhammad Shahir Rahman
  • Patent number: 10860768
    Abstract: Disclosed herein are embodiments of tools and techniques for computing the electric coupling in terms of parasitic admittance and capacitance values between a through silicon via (TSV) and surrounding interconnect of an integrated circuit layout design. In particular embodiments, a computation of one or more admittance and capacitance values between a through-silicon-via (TSV) structure and an interconnect structure of the three-dimensional integrated circuit layout design using two or more field solvers or rule-based engines that are different from one another is performed. In addition, electrical connectivity for the coupling parasitic between a TSV and an interconnect is established. Then, a parasitic netlist representation of the three-dimensional integrated circuit layout design that includes the above parasitic element values is generated.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: December 8, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Vasileios Kourkoulos, Georgios Manetas
  • Patent number: 10846448
    Abstract: A system may include a quantum model engine configured to generate (e.g., load or instantiate) a quantum computing model to represent an electronic design automation (EDA) process for a circuit design. The EDA process may be a multi-patterning process to assign colors to geometric elements of the circuit design. The quantum computing model may include quantum particle types that may be defined to prohibit non-physical states in the quantum computing model from occurring. The quantum model engine may also be configured to generate a color assignment for the geometric elements of the circuit design through the quantum computing model. The system may also include a manufacture support engine configured to use the color assignment to support manufacture of circuit layers of the circuit design through multiple manufacturing steps.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 24, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Fedor G. Pikus, Shashank Jaiswal
  • Patent number: 10830815
    Abstract: A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of “1” and a specified value of “0” for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: November 10, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Yu Huang