Abstract: A hardware model of a memory comprises: first circuitry configured to supply a memory status value for the memory which is changed upon a full-memory erase operation; second circuitry configured to supply a sector status value for each memory sector of the memory which is changed to a value equal to the memory status value when a write operation is performed on the each memory sector of the memory; and third circuitry configured to supply, when a read operation is performed on a memory sector of the memory, a value stored in the memory sector as output of the read operation if the sector status value for the memory sector is equal to the memory status value or a predefined value as the output of the read operation in other situations.

Abstract: Aspects of the disclosed technology relate to techniques of voltage propagation-based reliability verification. Voltage values are propagated across components of a circuit design through global iterations until voltage values on nets of the circuit design are not changed from one global iteration to a next global iteration or one preset condition is met. At least one of the global iterations comprises local iterations for a subcircuit of the circuit design. The local iterations suspend when voltage values on nets of the subcircuit are not changed from one local iteration to a next local iteration or one preset condition is met. The propagated voltage values are then analyzed to detect problems in the circuit design.

Abstract: A system, method and computer program product are provided for conditionally eliminating a memory read request. In use, a memory read request is identified. Additionally, it is determined whether the memory read request is an unnecessary memory read request. Further, the memory read request is conditionally eliminated, based on the determination.

Abstract: Low power very large scale integrated (VLSI) designs using a circuit failure in sequential cells as low voltage check for limit of operation of a design are provided. One such method involves the adding a plurality of bits for sequential elements in the design including sets of flip-flops, RAMs, ROMs and register files to add parity or single error correct and double error detect mechanism, a method to detect the parity errors or a single bit error and a double bit error in the sequential elements, starting at a voltage of operation at a nominal value and gradually lowering voltage setting till a first error is detected in the sequential elements, increasing the voltage of operation by predetermined step above a voltage of first fail to achieve an optimal voltage setting of a correct operation of the design, storing this optimal voltage setting in anon-volatile memory for a subsequent use.

Abstract: This application discloses a computing system to implement object tracking in an assisted or automated driving system of a vehicle. The computing system can assign a pre-classification to a detection event in an environmental model, update the environmental model with new sensor measurements and corresponding detection events over time, and track the detection event in the updated environmental model. The computing system can track the detection event by predicting a future state of the detection event with a state change model selected based on the assigned pre-classification, comparing the predicted future state to an actual future state of the detection event in an update to the environmental model, and determining the detection event corresponds to an object proximate to the vehicle based on the comparison. A control system for the vehicle can control operation of the vehicle based, at least in part, on the tracked detection event.

Abstract: This application discloses performing functional verification on a circuit design describing an electronic device and a computing system to determine occurrences of coverpoints and coverage crosses within a covergroup based on the results of the functional verification of the circuit design. Each coverpoint corresponds to a signal state or a variable value in the circuit design during the functional verification. Each of the coverage crosses corresponds to a different plurality of the coverpoints occurring concurrently. The computing system can generate a graphical presentation of the covergroup. The graphical presentation include nodes, each of which corresponding to the coverpoints or the coverage crosses. The nodes can be arranged in the graphical presentation based on connectivity between the coverpoints and the coverage crosses and clustered in the graphical presentation based on the occurrences of the coverpoints and coverage crosses during the functional verification of the circuit design.

Abstract: Traffic-shaping information is associated with ingress transaction-level messages by a traffic generation device. The ingress transaction-level messages and the traffic-shaping information are then sent to a reconfigurable hardware modeling device. The ingress transaction-level messages are converted to ingress signal-level messages by a hardware model of interface circuitry implemented in the reconfigurable hardware modeling device. Based on the traffic-shaping information, the ingress signal-level messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device.

Abstract: A reconfigurable scan network in a circuit is configured such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault. A test pattern having a length equal to a length of the second path is shifted into the reconfigurable scan network, and a part or a whole of the test pattern is then shifted out from the reconfigurable scan network. The part or the whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level (“RTL”) circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.

Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.

Abstract: An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable media. The part or the whole of the emulation process is then repeated with the emulator decoupled to the one or more targets. During the repeating, the input signals stored in the one or more processor-readable media are being streamed back to the emulator. The streaming in both of the capture and replay modes may be through interfaces designed for small packets of data and fast streaming speed.

Abstract: Disclosed are techniques for processing layout designs based on dynamically-generated lithographic models. Lithographic models are determined for a plurality of regions of a reticle prior to lithographic simulation. During lithographic simulation, lithographic models for a small area within a particular region are generated based on the lithographic models for the particular region, the lithographic models for one or more neighboring regions, and location information of the small area relative to the region and to the one or more neighboring regions. The lithography models comprise illuminating and imaging system models and mask electro-magnetic field models.

Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes.

Abstract: Aspects of the disclosed technology relate to techniques of context-aware pattern matching and processing. A circuit design is analyzed to identity circuit components of interest. Reference layout patterns that are associated with the circuit components of interest are extracted from a layout design based on the association of circuit components of the circuit design with geometric elements of the layout design. Pattern matching is performed to identify layout patterns that match the reference layout patterns. The identified layout patterns are then processed.

Abstract: Various aspects of the disclosed technology relate to generating streaming data and configuration data for streaming networks in circuits. Configuration information for transporting data in a first network to the plurality of circuit blocks in a circuit is determined based on information of the plurality of circuit blocks, information of the first network, the data, user-provided information, or any combination thereof. Sets of data packets are generated from the data based on the configuration information. Each set of the sets of data packets comprises equal-sized data packets to be transported consecutively in the first network. Configuration data to be transported in a second network in the circuit is also generated based on the configuration information. The configuration data comprises data for configuring first interface devices comprised in the first network.

Abstract: Various aspects of the disclosed technology relate to streaming data for testing identical circuit blocks in a circuit. The system for streaming data comprises a first network for transporting equal-sized data packets consecutively and a second network for configuring interface devices of the first network. Each of the data packets comprises bits of test patterns and bits of good-machine test responses. Comparison bits (pass/fail status bits) of an identical circuit block instance may be unloaded directly or may merge with those from other identical circuit block instances to generate accumulated comparison bits which are unloaded. A sticky pass/fail bit may also be generated for each of the identical circuit block instances.

Abstract: Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques. Locations in a circuit design for inserting test points are determined based on internal signal conflicts caused by detecting multiple faults with a single test pattern. Test points are then inserted at the locations. The internal signal conflicts may comprise horizontal conflicts, vertical conflicts, or both. The test points may comprise control points, observation points, or both.

Abstract: This application discloses web or cloud-based electronic design automation tools, which can incorporate functionality to enable collaborative and/or social interaction among multiple different users of the electronic design automation tools. The electronic design automation tools can monitor activity of a user on a design tool, compare the activity of the user on the design tool to previous design activities of one or more different users of the design tool, and prompt presentation of a design suggestion to the user based, at least in part, on a commonality between the activity of the user and previous design activities of the one or more different users.

Abstract: Methods and apparatus are disclosed for symbolic methods using algebraic geometry (e.g., based on a Gröbner basis of tangent space polynomials of parametric curves). For example, the design, optimization and verification of silicon photonic wave guides using parametric polynomials and/or Gröbner basis functions can be used to perform envelope generation, rectification, manufacturability checking, singularity detection, reticle and etch processing model generation, tapering loss minimization, and bend loss minimization. In one example, a method of analyzing a layout to be manufactured using a photolithographic process includes producing an envelope of a curve representing a layout object based at least in part on a Gröbner basis and performing one or more analysis operations for the envelope to perform verification and manufacturability checks.