Abstract: This application discloses a computing system to receive a specification of prototype wiring corresponding to a signal in a logical design of a wire harness, locate a section of a vehicle to include a portion of the wire harness corresponding to the signal in the logical design, and insert the prototype wiring into a physical design of the wire harness corresponding to the located section of the vehicle. The specification of the prototype wiring can identify a particular vehicle configuration and insert the prototype wiring into a physical design of the wire harness for the particular vehicle configuration. The computing system can receive constraints configured to control synthesis of the logical design into the physical design of the wire harness, and generate portions of the physical design of the wire harness based on the constraints, while retaining the prototype wiring that was inserted into the physical design.

Abstract: This application discloses a design verification tool implementing in a functional verification environment with a computing system, a hardware emulator, or a combination thereof. The design verification tool can identify, from a power intent specification of a circuit design, operational states of circuitry described in the circuit design, and generate code coverage bins based on the operational states of the circuitry. The operational states of the circuitry correspond to operational capabilities of the circuitry supported by each of the power modes for the circuitry. The code coverage bins are configured to store code coverage events occurring when the circuitry operates in different power modes. The design verification tool can utilize the code coverage bins to record the code coverage events performed by the circuitry during functional verification operations in a verification environment, and also can generate at least one coverage metric based on the records of the code coverage events.

Abstract: Simulation waveforms representative of simulation progress are generated and outputted for display. A netlist describing a circuit is accessed, and the circuit is simulated over a simulation runtime period. A simulation completion measurement is determined for the simulation runtime period, and a simulation waveform is generated based on the determined simulation completion measurement. Other simulation waveforms can be generated, for instance waveforms representative of a processing resource load over the simulation runtime period. Multiple simulation waveforms can be correlated and displayed in conjunction with each other, for instance in a common waveform interface.

Abstract: A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data.

Abstract: This application discloses a computing system to check and generate an assertion statement. The assertion statement, when executed during a simulation of a circuit design, can verify a simulated behavior of the circuit design. The computing system can extract sequence items from the assertion statement, and generate a state representation for the sequence items based on the simulated behavior of the circuit design. The state representation can identify states of the extracted sequence items at different clock ticks of the simulation. The computing system can locate an error in the assertion statement based on the state representation by generating patterns from sequence operators in the assertion statement and comparing the patterns to the state representation. The computing system can utilize the error in the assertion statement to generate a corrected assertion statement.

Abstract: Aspects of the disclosed technology relate to techniques of parasitic extraction using compact representation of process calibration data. Geometric information of a layout feature in the layout design comprising geometric parameters is extracted. Parasitic values associated with the layout feature are then computed based on the geometric information and one or more executable files selected in a plurality of executable files which are a compact representation of process calibration data.

Abstract: Logic diagnosis is performed on failing reports of defective integrated circuits to derive a diagnosis report for each of the failing reports which comprise information of suspects. The suspects comprise cell internal suspects and interconnect suspects. A probability distribution of root causes for causing the defective integrated circuits is determined to maximize a likelihood of observing the diagnosis reports based on a probability for each of the suspects given each of the root causes and a probability for each of the diagnosis reports given each of the suspects. The probability for each of the diagnosis reports given each of the cell internal suspects is weighted higher than the probability for each of the diagnosis reports given each of the interconnect suspects.

Abstract: This application discloses a computing system that can enter into a low power mode, shut down all components except for memory, and exit from the low power mode and restore running programs where they left off before entering the low power mode. To enter the low power mode, a processing device, in a user mode, can store program information to a memory. The processing device can switch to a hypervisor mode and store processor state information to a reserved portion of the main memory. The computing system can then disable hardware components of the computing system. To exit the low power mode, the computing system can enable the hardware components of the computing system, and activate the hypervisor mode of the processing device, allowing retrieval of the processor state information. The processing device can switch to the user mode and load stored the program information from the main memory.

Abstract: This application discloses a computing system to implement vehicle localization in an assisted or automated driving system. The computing system can receive an environmental model populated with measurement data captured by sensors mounted in a vehicle. The computing system can detect a location of the vehicle relative to the map data based on a correlation between the measurement data and the map data. The computing system can detect landmarks in the map data and switch to sparsely-populated map data from higher-definition map data for subsequent location detections. When the computing system does not detect a vehicle location, the computing system can track movement of the vehicle based on subsequent measurement data in the environmental model. After reacquiring a vehicle location, the computing can realign the tracked movement of the vehicle and measured data to the map data or modify the map data to include the tracked data.

Abstract: This application discloses a computing system configured to crop a layout design for an electronic device implemented with a layered interconnect, place a termination structure corresponding to a resistive sheet or a set of resistive components on an artificial boundary corresponding to an edge in the cropped portion of the layout design, and generate an electrical model of a signaling net in the cropped portion of the layout design by generating mesh elements on a surface area of the cropped portion of the layout design including the termination structure and utilizing a field solver implementing a Boundary Element Method based analysis to solve integral forms of Maxwell's equations corresponding to the mesh elements. The electrical model of the signaling net in the cropped portion of the layout design can include a set of scattering parameters for the signaling net in the cropped portion of the layout design.

Abstract: Various aspects of the present disclosed technology relate to techniques for selective conditional stall for speeding up hardware-based circuit verification. A path-breaking circuit device is inserted into a location of a design path configured to generate a stall signal indicating whether a change of signal between a pair of neighboring clock cycles of a clock signal is detected at the location. The stall signal is used to directly or indirectly suppress, when the change of signal between the pair of neighboring clock cycles is detected, the next state updating for state element models in the hardware model of circuit design. The design path is usually the critical design path. The insertion location is usually selected to be a location where the signal does not change frequently.

Abstract: A system for processing messages of a high rate data stream and an apparatus including: a message processor including a plurality of processor sub-modules and configured to read an input data stream, process the input data stream, and to output an output data stream; at least one payload memory storing data related to the input data stream and accessible to the message processor; at least one instruction memory accessible to the message processor and storing computer program instructions configuring the message processor to process the input data stream; and an application processor configured to rewrite the at least one instruction memory.

Abstract: A thermal transient response simulation is performed for a structure having a plurality of thermal model elements. The thermal transient response simulation determines a relation between transient thermal impedance of the structure and time and a relation between maximum temperature change of each of the thermal model elements and time. An onset time at which energy reaches each of the thermal model elements is determined based on the relation between maximum temperature change of each of the thermal model elements and time and a predetermined maximum temperature change threshold. An influence onset resistance value for each of the thermal model elements is determined by looking up a thermal resistance value corresponding to the onset time based on the relation between transient thermal impedance of the structure and time. A structural function is mapped based on the influence onset resistance value for each of the thermal model elements.

Abstract: This application discloses a computing system having a virtual machine and a host program that communicate via a virtual interface. The virtual machine can generate a data packet for transmission to the host program via the virtual interface. The virtual machine can receive a saturation signal generated by a virtual interface driver in the virtual interface. The virtual interface driver can be configured to populate a virtual buffer in the virtual interface with the data packet. The virtual machine can determine an availability of resources in the virtual buffer to store the data packet based, at least in part, on the saturation signal, and selectively stall transmission of the data packet to the host program based, at least in part, on the saturation signal. The host program can bypass a hypervisor in the computing system to directly access the virtual buffer in the virtual interface.

Abstract: This application discloses a computing system to export route data and connectivity data from a layout design of a package device. The route data describes a structure of an interconnect in the package device. The connectivity data characterizes an electrical interface between a first integrated circuit and the package device in the layout design. The computing system, based on the connectivity data associated with the first integrated circuit, can correlate the route data to pins of a second integrated circuit and identify net names for the route data and the second integrated circuit. The computing system can import the route data and the connectivity data to the layout design, which selectively realigns the route data in the layout design with the pins in the second integrated circuit, and also can allow the computing system to change net names corresponding to the route data connecting to the second integrated circuit.

Abstract: This application discloses an electronic control unit coupled to a bus in a vehicle communication network. The electronic control unit includes a processing system configured to generate an instruction including an identifier of a type of signal exchanged through a vehicle communication network and including a command associated with exchange of a signal value corresponding to the type of the signal. The electronic control unit includes a communication circuitry configured to identify, based on the type of the signal in the instruction, a packet having a section allocated for the signal value corresponding to the type of the signal. The communication circuitry also can perform packet operations on the section of the packet allocated for the signal value based, at least in part, on the command included in the instruction. The packet operations can include packing the signal value into the packet or extracting the signal value from the packet.

Abstract: This application discloses a computing system to implement map building in an assisted or automated driving system. The computing system can track movement of a vehicle based on sensor measurement data populated in an environmental model and vehicle movement measurements. The computing system can correlate the tracked movement of the vehicle to map data based on a previously detected location of the vehicle relative to the map data. The computing system can modify the map data to include the sensor measurement data utilized to track the movement of the vehicle based on the correlation of the tracked movement of the vehicle to map data. The computing system can modify the map data by building a map of the sensor measurement data and the tracked movement of the vehicle, and populating the map data with the built map.

Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.

Abstract: Disclosed herein are representative embodiments of methods, systems, and apparatus that can used to control real-time events (e.g., the real-time clock) during the design, simulation, or verification of an embedded system. In one exemplary embodiment disclosed herein, for example, a real-time clock signal is generated and tasks defined by an embedded software application are triggered with the real-time clock signal. In this embodiment, the embedded software application is executed by an embedded processor with a real-time operating system (“RTOS”), and the real-time clock signal is controllable independent of a processor clock signal driving the embedded processor in a manner that allows the real-time clock to have a different time base than the processor clock.

Abstract: Aspects of technology disclosed herein relate to techniques of a full-circuit simulation-based circuit design verification. A simulation is performed to determine current data of parasitic resistors in one or more parasitic resistance networks in power supply circuitry of a circuit design by injecting a current into each one of the one or more parasitic resistance networks. Based on the current data, non-current carrying parasitic resistors are removed from the one or more parasitic resistance network to generate one or more reduced parasitic resistance network. Using the one or more reduced parasitic resistance networks, a full-circuit simulation is performed to obtain current density information. A circuit design verification of the circuit design is then performed based on the current density information.