Abstract: Various aspects of the disclosed technology relate to techniques of retargeting layout features. A process window simulation on a layout design is performed to generate process window information that comprises predicted print positions of layout features computed under various process conditions. Retargeted print positions for a plurality of edge fragments in the layout design are then determined based on minimizing a combined change of targeted print positions for the plurality of edge fragments under constraints represented based on the process window information and specification limits for printed layout features. Based on the retargeted print positions, positions of the plurality of edge fragments are adjusted for optical proximity correction.

Abstract: Tools and methods for profiling power consumption of an embedded system are provided. Power event and control modules, executable by the embedded system are provided. Additionally, a power measurement and control unit is provided that can measure the power consumption and limit the supply current to the embedded system. Furthermore, a power profiling tool is provided. The tool includes modules that interface with the power measurement and control unit and well as the power event and control modules. Then, power event and system data may be received by the power profiling tool from the embedded system and power consumption data may be received from the power measurement and control unit. Subsequently, power consumption metrics may be viewed by the power profiling tool.

Abstract: This application discloses a computing system to pre-process a physical or geometric layout of a circuit design to determine various attributes of the nets, such as a location and a total capacitance for each net in the geometric layout. The computing system can order extraction of the nets from the geometric layout of the circuit design with a space filling curve based, at least in part, on the locations of the nets in the geometric layout of the circuit design and any coupling capacitance between the nets in the geometric layout of the circuit design. The computing system can selectively decouple nets with a coupling capacitance based, at least in part, on the total capacitance for the nets associated with the coupling capacitance. The computing system can generate an electrical representation for each of the extracted nets and write them to a netlist for the circuit design.

Abstract: Aspects of the invention relate to techniques for determining pattern optical similarity in lithography. Optical kernel strength values for a first set of layout features and a second set of layout features are computed first. Based on the optical kernel strength values, optical similarity values between the first set of layout features and the second set of layout features are then determined. Subsequently, calibration weight values for the first set of layout features may be determined based on the optical similarity values, which, along with the first set of layout features, may be employed to calibrate lithography process model parameters.

Abstract: Aspects of the disclosed technology relate to techniques of connectivity-aware reduction of layout data. With various implementations of the disclosed technology, circuit elements of interest are selected in a circuit design which includes netlist information and layout data. Based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, nets of interest are determined. Cells of interest, comprising cells that are identified based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, are then determined. Based on the nets of interest and the cells of interest, layout geometric elements are selected and may be analyzed for design verification. For electrostatic discharge (ESD) protection verification, the cells of interest may further comprise cells that include portions of power supply grids on top metal layers.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: This application discloses a computing system implementing tools and mechanisms to generate a framework for a system-level design of an electronic system, wherein the system-level design includes multiple electronic designs from different electronic design automation tools. The tools and mechanisms can correlate design components in the electronic designs to different portions of the framework for the system-level design, and determine whether the electronic designs are congruent with the system-level design based, at least in part, on the correlation of the electronic designs to the different portions of the framework for the system-level design.

Abstract: A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.

Abstract: An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable media. The part or the whole of the emulation process is then repeated with the emulator decoupled to the one or more targets. During the repeating, the input signals stored in the one or more processor-readable media are being streamed back to the emulator. The streaming in both of the capture and replay modes may be through interfaces designed for small packets of data and fast streaming speed.

Abstract: An event management structure for an embedded system, which supports multiple waiters waiting on the same event without replicating the events for each waiter, is provided. Notifications of events are received from entities within an embedded system. The event management architecture then posts the events to a central queue and generates a unique identification tag for each posted event. Additionally, entities within the embedded system are allowed to wait on specific events. More specifically, entities may request access to specific events based on the unique identification tag associated with a particular event. In further implementations, data associated with queued events may be provided to the waiters. In some implementations, events matching a specific description since a particular event, identified by its unique identification tag, may be requested by entities in the embedded system.

Abstract: In one embodiment, a method for building a clock tree for an integrated circuit design is provided. The clock tree may include a clock tree root node and a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design. The clock tree nodes may be arranged to distribute the clock signal to the sink pins. In synthesizing the clock tree, the sink pins may be clustered into one or more clusters. Clock tree nodes may be placed for the clock tree to distribute the clock signal to the one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters. For example, the clock tree timing variation parameters includes timing information for multiple process corners and/or multiple modes of operation.

Abstract: Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information.

Abstract: Various aspects of the disclosed technology relate to techniques of determining an across-chip distribution of temperature generated by on-chip devices. Effective thermal conductance and effective thermal capacity for each region of a plurality of regions of a layout design are first extracted. The effective thermal conductance for a region in a metal layer is determined based at least on density information of metal interconnect lines within the region and has components associated with directions of the metal interconnect lines. A thermal circuit is then constructed based on the effective thermal conductance, the effective thermal capacity and heat information of thermal nodes. The heat information of thermal nodes is determined based on an electrical simulation on the integrated circuit associated with the layout design. A thermal simulation is then performed on the thermal circuit to determine temperature information of the thermal nodes.

Abstract: A method and apparatus applies an action to a software application by determining a target object for the input action. The determination of the target object is performed by identifying the target object through socially identifying object information relative to a reference object. Then, the input action is applied to the target object.

Abstract: This application discloses a computing system implementing tools and mechanisms to generate a framework for a system-level design of an electronic system, wherein the system-level design includes multiple electronic designs from different electronic design automation tools. The tools and mechanisms can correlate design components in the electronic designs to different portions of the framework for the system-level design, and determine whether the electronic designs are congruent with the system-level design based, at least in part, on the correlation of the electronic designs to the different portions of the framework for the system-level design.

Abstract: This application discloses a computing system implementing tools and mechanisms to generate a framework for a system-level design of an electronic system, wherein the system-level design includes multiple electronic designs from different electronic design automation tools. The tools and mechanisms can correlate design components in the electronic designs to different portions of the framework for the system-level design, and determine whether the electronic designs are congruent with the system-level design based, at least in part, on the correlation of the electronic designs to the different portions of the framework for the system-level design.

Abstract: This application discloses a computing system implementing tools and mechanisms that can incorporate an optical physical uncloneable function (PUF) device in a circuit design. The optical physical uncloneable function device can generate at least a portion of a key. The tools and mechanisms can interconnect the optical physical uncloneable function device with a security control device in the circuit design, wherein the security control device is configured to initiate a security action when the key matches an expected key in the security controller.

Abstract: Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.

Abstract: Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element.

Abstract: Aspects of the invention relate to scan-based test architecture for interconnects in stacked designs. The disclosed scan-based test architecture comprises a scan chain. Scan cells on the scan chain are configured to receive data from, based on bits of a control signal, outputs of neighboring scan cells or outputs of mixing devices that combine data from through-silicon vias with data from the outputs of the neighboring scan cells. The scan-based test architecture can be used to identify single or multiple defective through-silicon vias.