Abstract: A method includes detecting a power-up event associated with a memory sub-system comprising a plurality of blocks of memory cells having blocks of memory cells associated therewith, responsive to detecting the power-up event and prior to receipt of signaling indicative of a host initiation sequence, determining that a block of memory cells associated with a respective block among the plurality of blocks of memory cells is an open virtual block of memory cells, determining that the respective block associated with the open virtual block of memory cells exhibits greater than a threshold health characteristic value, and selectively performing a media management operation of a respective block of memory cells associated with the open virtual block of memory cells in response to the determination that the respective block exhibits greater than the threshold health characteristic value.

Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Abstract: A die casting insert for producing die casted metal parts from liquid metal. The die casting insert has an outer casing shaped to be fixed in the die block of the die casting apparatus. The die casting insert also has a stopper with a purge opening that is adapted to evacuate contaminants topping the liquid metal as pressure is applied to the liquid metal. The stopper, fitted to mate with the hollow inner cavity of the injection sleeve, is constructed to seal the hollow inner cavity of the injection sleeve except at the purge opening when in a first position; and to permit the flow of the liquid metal into at least one molding cavity when the stopper is in a second position. The die casting insert also has an activation mechanism configured to shift the stopper between the first position and the second position.

Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

Abstract: A dispensing apparatus including a body having an open end and a closed end; a first channel and a second channel within the body, the first and second channels sharing a sidewall and the first channel defining the open end; and a wire disposed within the first and second channels. This disclosure also discloses a dispensing apparatus including a body having an open end and a closed end and a first layer and a second layer; a first channel and a second channel within the first layer and a third channel and a fourth channel within the second layer, the first channel defining the open end; a transitional segment providing fluid communication between the first and second layers; and a wire disposed within the first, second, third, and fourth channels.

Abstract: A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. The first molding compound is disposed over the first redistribution layer and surrounds the semiconductor device. The second molding compound surrounds the first redistribution layer and at least a part of the first molding compound. The conductive vias extend through the second molding compound. The second redistribution layer is disposed on a surface of the second molding compound away from the first redistribution layer. The second redistribution layer is electrically connected to the first redistribution layer through the conductive vias.

Abstract: Methods of operating memory, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a particular memory cell of the memory, programming additional data to the particular memory cell, determining if a power loss to the memory is indicated while programming the additional data to the particular memory cell, and, if a power loss to the memory is indicated, selectively programming one memory cell of a pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell. A resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells is representative of the information indicative of the data value stored in the particular memory cell.

Abstract: Apparatuses and methods related to performing logical operations using sensing circuitry are provided. One apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. The sensing circuitry includes a sense amplifier and does not include an accumulator. The controller is configured to perform logical operations using the array of memory cells as an accumulator without transferring data out of the memory array and sensing circuitry.

Abstract: A potentiometric sensor, comprising: a potentiometer track; a collector track opposite the potentiometer track; a conductive magnetic cushion slider coupled to the potentiometer track and the collector track; and a sealed body housing the potentiometer track, the collector track, and the conductive magnetic cushion is disclosed. The potentiometric sensor may provide a variable output voltage indicative of a level of liquid in a container. The output voltage of the potentiometric sensor may be based on a position of a magnet, which may determine a position of the conductive magnetic cushion or a ferromagnetic spring. The magnet may be outside of the sealed body. As the sensor will be more cost effective and less space consuming, the totally sealed sensor incorporating the conductive magnetic cushion or a ferromagnetic spring may replace many applications that allow a hysteresis of less than 1 mm. Additionally, these applications may be used on rotary systems.

Abstract: A die casting insert for producing die casted metal parts from liquid metal. The die casting insert has an outer casing shaped to be fixed in the die block of the die casting apparatus. The die casting insert also has a stopper with a purge opening that is adapted to evacuate contaminants topping the liquid metal as pressure is applied to the liquid metal. The stopper, fitted to mate with the hollow inner cavity of the injection sleeve, is constructed to seal the hollow inner cavity of the injection sleeve except at the purge opening when in a first position; and to permit the flow of the liquid metal into at least one molding cavity when the stopper is in a second position. The die casting insert also has an activation mechanism configured to shift the stopper between the first position and the second position.

Abstract: Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells.

Abstract: Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another.

Abstract: Content addressable memory (CAM) devices provide for high density, low cost CAM devices. CAM devices include a non-volatile memory array having a plurality of NAND memory cell strings, wherein a NAND memory cell string of the non-volatile memory array comprises a plurality of CAM memory cells, and wherein the CAM memory cells comprise non-volatile memory cells of a same NAND memory cell string. The CAM devices further include a control circuit, wherein the control circuit is adapted to search data words stored in the plurality of NAND memory cell strings for a match to at least a portion of an input data word.

Abstract: Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.

Abstract: A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor.

Abstract: Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract: A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems.

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

Abstract: Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming; and applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage.