Abstract: A method and device for providing a relief area on the surface of a molded I/C package. Specifically, a method of reducing delamination at the gate area of a molded I/C package by disposing an area of patterned metal traces on the substrate surface to form a relief area. The relief area will permit the I/C package to be broken away form the molding apparatus while reducing the possibility of delamination or Au/Cu burs at the gate area.

Abstract: Elastomer thin films can be lithographically patterned by using an UV curable polydimethylsiloxane, rather than replica molding of thermal cure elastomers. The fabrication method of such patterned elastomers consists of elastomer formulation, substrate modification, spinning elastomer, pattern development, and possible a backside etch of the substrate.

Abstract: A sequence of MEMS processing steps are used to construct a 2D optical switch on a single substrate. In a typical optical switch configuration, an array of hinged micromirrors are supported by an array of posts at a 45° angle to the input and output optical paths and positioned parallel to the substrate either above, below or, perhaps, in the optical paths. The application of a voltage between the mirror and its control electrodes switches the mirror to a vertical position where it intercepts and deflects light travelling down the optical paths. The posts are suitably oriented at a 90° angle with respect to the mirror hinges so that they do not interfere with the optical paths and, may be configured to function as baffles to reduce crosstalk between adjacent optical paths.

Abstract: An array of micromachined mirrors are arranged on a first substrate at the intersections of input and output optical paths and oriented at approximately forty-five degrees to the paths. An array of split-electrodes are arranged on a second substrate above the respective mirrors. Each split electrode includes a first electrode configured to apply an electrostatic force that rotates the mirror approximately ninety degrees into one of the input optical paths to deflect the optical signal along one of the output optical paths, and a second electrode configured to apply an electrostatic force that maintains the mirror position. Stability may be improved by using the first and second electrodes in combination to first actuate the mirror and then balance the forces on the mirror to maintain its position. Reproducibly accurate positioning of the mirrors requires either the use of active positioning control or of mechanical stops.

Abstract: A low cost waveguide tunable Bragg grating provides a flat passband and minimal crosstalk. A compliant material forms a waveguide that is imprinted with a Bragg grating and mounted on a MEMS actuator. Entropic materials such as elastomers, aerogels or other long-chain polymers may provide the necessary compliance. The application of a drive signal to the actuator deforms (squeezes or stretches) the compliant material thereby changing the Bragg spacing and shifting the resonant wavelength. The MEMS actuator can be an electrostatically or electromagnetically actuated comb-drive.

Abstract: A cost-effective tunable optical component uses entropic, rather than enthalpic, materials to provide a compliant member that supports the optical element and is driven by an electrostatic actuator. Entropic materials exhibit an entropic plateau region over a wide frequency range with a Young's modulus much lower than enthalpic materials, linear elastic behavior over a wide deformation range, and, in certain geometries, energy and stress behavior that tend to stabilize the optical element during deformation. The compliant member can be configured in a variety of geometries including compression, tension, tensile/compressive and shear and of a variety of materials including elastomers, aerogels or other long chained polymers.

Abstract: A system for interfacing a human user to a data processor which receives inputs from the user and includes associated storage resource information. The data processor generates outputs to the user and associated output devices. The interface system includes structure for receiving a statement generated by the human user in natural language on a word-by-word basis. The system analyzes the statement to identify a subject and object and searches the stored resource information for data related to the identified subject. Output devices are provided for generating to the user the data from the stored resource information related to the identified subject.

Abstract: A memory device which includes intermediate storage, or cache, and unidirectional data paths coupling the intermediate storage to external input/output. The invention improves the response of the memory device by eliminating dual latencies associated with the transition from a write request to a read request. The method of use of the invention and systems incorporating the invention are further described.

Abstract: A method of applying a dispersion (which may be in the form of a paste) of particles of a thermoplastic polymer in a liquid medium (i.e., liquid carrier) onto semiconductor wafers, dies, lead frames, and printed circuit boards, for example, to form bonding layers, pads, and bumps, etc.

Abstract: A membrane-actuated charge controlled mirror (CCM) that exhibits increased deflection range, reduced beam current and improved electrostatic stability is fabricated using a combination of flat panel manufacturing along with traditional MEMS techniques. More specifically, a unique combination of five masking layers is used to fabricate a number of CCMs on a large glass panel. At the completion of the MEMS processing, the glass panel is diced into individual CCMs. Thereafter, the polymer mirror and membrane release layers are simultaneously released through vent holes in the membrane to leave the free-standing CCM.

Abstract: A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transistors of adjacent memory cells, and a pair of word lines are located in each of the isolation trenches. The word lines are oriented vertically widthwise in the trench and are adapted to gate alternate access transistors, so that both an active and a passing word line can be contained within each memory cell to provide a folded bit line architecture. The memory cell has a surface area that is approximately 4 F.sup.2, where F is a minimum feature size. Also disclosed are processes for fabricating the DRAM cell using bulk silicon or a silicon on insulator processing techniques.

Abstract: The present invention comprises a metallization method that forms a three-level interconnect in an electrical circuit. The method comprises providing a substrate assembly and depositing thereon a first dielectric layer thereover. A second dielectric layer is then deposited over the first dielectric layer. The second dielectric layer is patterned and anisotropically etched to form contact corridors. The second dielectric layer is again patterned and etched to form trenches, some of which are immediately above the contact corridors. An electrically conductive material is deposited to fill the contact corridors and trenches, and to leave a portion of the electrically conductive material above the second dielectric layer and directly above both the contact corridors and the trenches. The deposition forms a unitary three-level interconnect having a contiguous trench below a contact corridor below a metal line, where the metal line is above the second dielectric layer.

Abstract: A pull-down circuit in a sense amplifier, such a sense amplifier in a memory integrated circuit, includes a pull-down transistor having a drain coupled to a common node, a gate, and a source coupled to ground. An inverter provides a gate control signal to the gate of the pull-down transistor. A choke transistor has a drain coupled to a power terminal of the inverter, a gate, and source coupled to the power supply voltage. A regressive drive bias circuit is coupled to the gate of the choke transistor and provides a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor and provides a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.

Abstract: A rotary coupling for use in an apparatus for chemical mechanical planarization of material substrates. The coupling has a housing defining a chamber therein. A housing passage is formed through the housing and communicates with the chamber and a fluid source. A rotary shaft is connected at one end to the apparatus and has at an opposite end a coupling end extending into the chamber. A shaft passage is formed longitudinally through the shaft which opens into the coupling end and communicates with the apparatus at its other end. A coupling interface is defined within the chamber of the housing for abutting against the shaft coupling end. The coupling end and coupling interface are biased against one another. The shaft passage and housing passage in combination define a portion of a continuous fluid process line between the apparatus and the fluid source.

Abstract: The present invention is directed to a novel apparatus for "on-the-fly" data correction and regeneration of a plurality of data read from and stored to a plurality of storage devices. A control circuit is provided for control of data flow to and from the storage devices. The control circuit establishes and maintains a relatively simple semaphore between itself and an interface circuit controlling a FIFO buffer. A mask register is provided as a type of programmable logic AND gate to assert a master ready signal when each of a selected plurality of the interface circuits, one interface circuit per FIFO buffer, indicates that its respective FIFO buffer is ready, either to output or input an entire block. When each is ready, routing and correction commences under control of the control circuit until an entire block has been processed. Each interface circuit includes an associated flip/flop having an output which provides an indication of the ready status.

Abstract: A system for interfacing a human user to a data processor which receives inputs from the user and includes associated storage resource information. The data processor generates outputs to the user and associated output devices. The interface system includes structure for receiving a statement generated by the human user in natural language on a word-by-word basis. The system analyzes the statement to identify a subject and object and searches the stored resource information for data related to the identified subject. Output devices are provided for generating to the user the data from the stored resource information related to the identified subject.

Abstract: A multiport switch buffers and transfers cells of digital data. It provides the ability to control the synchronization of the ports in a distributed manner. Each port is associated with a counter that starts counting when transmission by either the port it is associated with is transferring a cell, or when another port is transferring a cell on a channel that conflicts with the channel attached to the port. The counter counts the appropriate number of digits corresponding to the length of the cell whereupon the port is provided with a signal indicating that the transmission has ended. In association with other control signals, the port may then begin transmitting a new cell. When multiple switches are attached to the same channel, the counter serves as a self-queuing mechanism that relieves a central controller from having to keep track of the transmission of bits by each port, and from having to select the next port for transmission.

Abstract: A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a cover layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer.

Abstract: An electronic power supply for use with a gas discharge lamp, including a transformer having its primary winding connected in parallel with a capacitor of a series resonant element connected between an inverter and the lamp, effective to limit the voltage from the power supply to a predetermined level.

Abstract: An electronic ballast circuit for multiple fluorescent lamps. Control is achieved by varying the voltage and the frequency of operation of an inverter utilized to drive the fluorescent lamps. A separate voltage boost converter provides regulated voltage to the converter. Dimming is accomplished by varying the voltage either manually or in response to sensor circuitry.