Abstract: A method for making a metal-insulator-metal (MIM) capacitors by etching a dielectric layer to form a via or contact hole, a tub, and a trench in the dielectric layer; depositing conformal metal in the via or contact hole, the tub, and the trench, wherein deposited conformal metal forms a via or contact in the via or contact hole; depositing a bottom electrode metal in the tub to form a bottom electrode of a metal-to-metal (MIM) capacitor; removing bottom electrode metal from the bottom electrode to form a dish-shape upper surface; depositing an insulator material on the bottom electrode to form an insulator layer of the MIM capacitor; and depositing a top electrode metal on the insulator layer to form a top electrode of the MIM capacitor.

Abstract: A method for making a three dimensional (3D) Metal-Insulator-Metal (MIM) capacitor and trenches by etching a dielectric layer to form a via or contact hole, a tub, and a trench in the dielectric layer; depositing conformal metal in the via or contact hole, the tub, and the trench, wherein the deposited conformal metal forms bottom and sidewall portions of a 3D bottom electrode of a metal-insulator-metal (MIM) capacitor in the tub, and wherein the deposited conformal metal forms a via or contact in the via or contact hole; removing conformal metal and at least a portion of the dielectric layer from a lip of the tub; depositing an insulator layer on the 3D bottom electrode to form an insulator layer of the MIM capacitor; and depositing a metal layer on the insulator layer to form a top electrode of the MIM capacitor.

Abstract: Methods for preparing a donor silicon wafer by applying a SiGe layer on a silicon substrate wafer, depositing a silicon layer on the SiGe layer, etching the silicon layer to form an opening in the silicon layer, wet etching the SiGe layer through the opening in the silicon layer to partially remove SiGe material from the SiGe layer and preserve the silicon layer, depositing a buried oxide layer on the silicon layer, etching the buried oxide layer to form a body bias area, and depositing silicon in the body bias area; bonding a recipient handle wafer to the etched buried oxide layer of the donor silicon wafer to define a BOX; and wet etching the SiGe layer to release the donor silicon wafer from the recipient handle wafer.

Abstract: A process is provided for forming an integrated thin film resistor (TFR) in an integrated circuit (IC) device including IC elements and IC element contacts. A TFR film layer and TFR dielectric layer are formed over the IC structure, and a wet etch is performed to define a dielectric cap with sloped lateral edges over the TFR film layer. Exposed portions of the TFR film layer are etched to define a TFR element. A TFR contact etch forms contact openings over the TFR element, and a metal layer is formed to form metal layer connections to the IC element contacts and the TFR element. The sloped edges of the dielectric cap may improve the removal of metal adjacent the TFR element to prevent electrical shorts in the completed device. A TFR anneal to reduce a TCR of the TFR is performed at any suitable time before forming the metal layer.

Abstract: An electronic package includes a first integrated circuit (IC) die arranged in a first orientation, a second IC die arranged in a second orientation inverted relative to the first orientation, at least one upper conductive routing layer extending over the first IC die and second IC die, at least one lower conductive routing layer extending under the first IC die and second IC die, and a mold compound at least partially encapsulating the first IC die and the second IC die.

Abstract: A device having a processor and a boot code, the processor may create a plurality of revocation emulation containers corresponding to a plurality of owners of the electronic device over time, wherein respective revocation emulation containers may comprise asset revocation information associated with respective owners of the electronic device. The processor may program the asset revocation information of the plurality of revocation emulation containers in a one-time-programmable manner. The processor may use the asset revocation information of the plurality of revocation emulation containers to determine whether to revoke use of respective assets of a plurality of assets associated with the plurality of owners of the electronic device over time. The processor may revoke the subsequent use of respective assets of the plurality of assets associated with the plurality of owners of the electronic device over time based on a determination the respective asset should be revoked.

Abstract: Reduced complexity encoders and related systems, apparatuses, and methods are disclosed. An apparatus includes a data storage device and a processing circuitry. The data storage device is to store a first data part of a transmit data frame. The transmit data frame is received from one or more higher network layers that are higher than a physical layer. The transmit data frame includes the first data part and a second data part. The second data part includes data bits having known values. The processing circuitry is to retrieve the first data part of the transmit data frame from the data storage device and determine parity vectors for the transmit data frame independently of the second data part responsive to the first data part.

Abstract: One or more embodiments of a process for provisioning a headless WiFi device are disclosed, and systems, methods and devices for the same. The process of provisioning a headless WiFi device includes establishing a first communication link between the headless WiFi device and a provisioning WiFi device, the provisioning WiFi device including a physical user interface. The process also includes transmitting a provisioning data from the provisioning WiFi device to the headless WiFi device, via the first communication link. The process further includes transmitting, by the headless WiFi device on a channel corresponding to a channel identifier included with the provisioning data, a connection request for request to a WiFi router access point corresponding to a service set identifier (SSID) included with the provisioning data. Additionally, the process includes establishing a second communication link between the headless WiFi device and the WiFi router access point.

Abstract: A system having a camera to capture a scene image of a scene having an object as viewed from a perspective of an operator through a windscreen; a computer vision circuit to identify an object image corresponding to the object in the scene image captured by the camera; a marker generator circuit to generate a marker indicative of the identified object image and to determine a marker position in the operator's line of sight between the object and the operator; and a screen to display the generated marker in the marker position to appear associated with the identified object as viewed from the perspective of the operator through the windscreen. Also, methods for marking objects.

Abstract: An integrated circuit (IC) package includes a partial leadframe including (a) a shunt resistor leadframe element including a pair of shunt resistor contacts and a shunt resistor conductively connected between the pair of shunt resistor contacts and (b) at least one external contact leadframe element separate from the shunt resistor leadframe element, the at least one external contact leadframe element allowing external contact to the IC package. The IC package also a mold encapsulation formed over the shunt resistor leadframe element, wherein the pair of shunt resistor contacts are externally contactable through the mold encapsulation.

Abstract: A device comprising: a repository for an item, the repository having an item intake; a sensor that generates a signal corresponding to characteristics of an item in the repository; an artificial intelligence circuit that receives from the sensor the signal corresponding to characteristics of an item in the repository and that transmits an indicator signal indicative of the item in the repository; and an indicator that receives from the artificial intelligence circuit the indicator signal and that indicates the item in the repository based on the indicator signal.

Abstract: An apparatus comprising: a pin to connect to a resistor and a power source; a measurement circuit to measure a voltage at the pin; a circuit to determine a mapped identification value of the apparatus based upon the voltage at the pin, the mapped identification value coding the apparatus as an instance of a product from a set of products; and an authentication circuit. The authentication circuit: calculates an authentication code using the mapped identification value; and provides the authentication code to an authentication host upon request from the authentication host.

Abstract: A network-synchronization device may include a match filter. The match filter may be configured to generate events for synchronizing operation of elements of a network at least partially responsive to timing frames generated at a network switch. The events for synchronizing operation of the elements may include a first event generated at least partially responsive to first information associated with a first element and a second event generated at least partially responsive to second information associated with a second element. Related systems and methods are also disclosed.

Abstract: Apparatuses and methods related to a converter are disclosed. An apparatus includes a converter and a controller. The converter converts an input voltage potential to an output voltage potential. The input voltage potential and the output voltage potential include direct current (DC) voltage potentials. The controller generates pulse width modulation (PWM) signals responsive to a duty cycle control signal, controls the converter via the PWM signals in a buck mode when the duty cycle control signal is less than a predetermined maximum buck value, and controls the converter via the PWM signals in a cascaded buck-boost mode (CBB mode) when the duty cycle control signal is greater than the predetermined maximum buck value. A duty cycle of at least a portion of the PWM signals transitions linearly with the duty cycle control signal from the buck mode to the CBB mode.

Abstract: An device having an oscillator circuit modifiable between a first operating mode and a second operating mode, wherein the first operating mode has a first frequency accuracy and a first power consumption, wherein the second operating mode has a second frequency accuracy and a second power consumption, wherein the second frequency accuracy is more accurate than the first frequency accuracy and the second power consumption is higher than the first power consumption, and a control circuit in communication with the oscillator circuit to modify the operating mode of the oscillator circuit.

Abstract: One or more embodiments relate to a multi-bias mode current conveyor. Such a current conveyor may include an input terminal, a reference terminal, an output terminal, a first and second cascoded current mirrors, and a biasing circuit. The first cascoded current mirror and a second cascoded current mirror may be arranged as a current conveyor that is configured to provide an output current that a mirror of an input current. The biasing circuit may be configured to provide a bias voltage selectively exhibiting a first voltage level or a second voltage level. The bias voltage may be provided at least partially responsive to a state of the input current. The biasing circuit may be arranged to apply the bias voltage to at least one of the first cascoded current mirror or the second cascoded current mirror.

Abstract: A controller area network (CAN) transmitter includes an output stage circuit including a CANH port and a CANL port, and an input stage circuit configured to receive an input signal. The input signal is configured to indicate whether the output stage circuit is to provide dominant or recessive states. The CAN transmitter includes a cascode circuit configured to provide output signals on the output stage circuit to provide dominant or recessive states based on the input signal. The CAN transmitter includes a switch circuit configured to, based upon the input signal, switch the cascode circuit on and off.

Abstract: Ferroelectric random access memory (FRAM) capacitors and methods of forming FRAM capacitors are provided. An FRAM capacitor may be formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The FRAM capacitor may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode, forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element. The FRAM capacitor may form a component of an FRAM memory cell. For example, an FRAM memory cell may include one FRAM capacitor and one transistor (1T1C configuration) or two FRAM capacitors and two transistor (2T2C configuration).

Abstract: An obfuscation process is described for obfuscating a cryptographic parameter of cryptographic operations such as calculations used in elliptical curve cryptography and elliptical curve point multiplication. Such obfuscation processes may be used for obfuscating device characteristics that might otherwise disclose information about the cryptographic parameter, cryptographic operations or cryptographic operations more generally, such as information sometimes gleaned from side channel attacks and lattice attacks.

Abstract: An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.