Abstract: A system having a camera to capture a scene image of a scene having an object as viewed from a perspective of an operator through a windscreen; a computer vision circuit to identify an object image corresponding to the object in the scene image captured by the camera; a marker generator circuit to generate a marker indicative of the identified object image and to determine a marker position in the operator's line of sight between the object and the operator; and a screen to display the generated marker in the marker position to appear associated with the identified object as viewed from the perspective of the operator through the windscreen. Also, methods for marking objects.

Abstract: An integrated circuit (IC) package includes a partial leadframe including (a) a shunt resistor leadframe element including a pair of shunt resistor contacts and a shunt resistor conductively connected between the pair of shunt resistor contacts and (b) at least one external contact leadframe element separate from the shunt resistor leadframe element, the at least one external contact leadframe element allowing external contact to the IC package. The IC package also a mold encapsulation formed over the shunt resistor leadframe element, wherein the pair of shunt resistor contacts are externally contactable through the mold encapsulation.

Abstract: A device comprising: a repository for an item, the repository having an item intake; a sensor that generates a signal corresponding to characteristics of an item in the repository; an artificial intelligence circuit that receives from the sensor the signal corresponding to characteristics of an item in the repository and that transmits an indicator signal indicative of the item in the repository; and an indicator that receives from the artificial intelligence circuit the indicator signal and that indicates the item in the repository based on the indicator signal.

Abstract: An apparatus comprising: a pin to connect to a resistor and a power source; a measurement circuit to measure a voltage at the pin; a circuit to determine a mapped identification value of the apparatus based upon the voltage at the pin, the mapped identification value coding the apparatus as an instance of a product from a set of products; and an authentication circuit. The authentication circuit: calculates an authentication code using the mapped identification value; and provides the authentication code to an authentication host upon request from the authentication host.

Abstract: A network-synchronization device may include a match filter. The match filter may be configured to generate events for synchronizing operation of elements of a network at least partially responsive to timing frames generated at a network switch. The events for synchronizing operation of the elements may include a first event generated at least partially responsive to first information associated with a first element and a second event generated at least partially responsive to second information associated with a second element. Related systems and methods are also disclosed.

Abstract: Apparatuses and methods related to a converter are disclosed. An apparatus includes a converter and a controller. The converter converts an input voltage potential to an output voltage potential. The input voltage potential and the output voltage potential include direct current (DC) voltage potentials. The controller generates pulse width modulation (PWM) signals responsive to a duty cycle control signal, controls the converter via the PWM signals in a buck mode when the duty cycle control signal is less than a predetermined maximum buck value, and controls the converter via the PWM signals in a cascaded buck-boost mode (CBB mode) when the duty cycle control signal is greater than the predetermined maximum buck value. A duty cycle of at least a portion of the PWM signals transitions linearly with the duty cycle control signal from the buck mode to the CBB mode.

Abstract: An device having an oscillator circuit modifiable between a first operating mode and a second operating mode, wherein the first operating mode has a first frequency accuracy and a first power consumption, wherein the second operating mode has a second frequency accuracy and a second power consumption, wherein the second frequency accuracy is more accurate than the first frequency accuracy and the second power consumption is higher than the first power consumption, and a control circuit in communication with the oscillator circuit to modify the operating mode of the oscillator circuit.

Abstract: Ferroelectric random access memory (FRAM) capacitors and methods of forming FRAM capacitors are provided. An FRAM capacitor may be formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The FRAM capacitor may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode, forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element. The FRAM capacitor may form a component of an FRAM memory cell. For example, an FRAM memory cell may include one FRAM capacitor and one transistor (1T1C configuration) or two FRAM capacitors and two transistor (2T2C configuration).

Abstract: An obfuscation process is described for obfuscating a cryptographic parameter of cryptographic operations such as calculations used in elliptical curve cryptography and elliptical curve point multiplication. Such obfuscation processes may be used for obfuscating device characteristics that might otherwise disclose information about the cryptographic parameter, cryptographic operations or cryptographic operations more generally, such as information sometimes gleaned from side channel attacks and lattice attacks.

Abstract: One or more embodiments relate to a multi-bias mode current conveyor. Such a current conveyor may include an input terminal, a reference terminal, an output terminal, a first and second cascoded current mirrors, and a biasing circuit. The first cascoded current mirror and a second cascoded current mirror may be arranged as a current conveyor that is configured to provide an output current that a mirror of an input current. The biasing circuit may be configured to provide a bias voltage selectively exhibiting a first voltage level or a second voltage level. The bias voltage may be provided at least partially responsive to a state of the input current. The biasing circuit may be arranged to apply the bias voltage to at least one of the first cascoded current mirror or the second cascoded current mirror.

Abstract: An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.

Abstract: A controller area network (CAN) transmitter includes an output stage circuit including a CANH port and a CANL port, and an input stage circuit configured to receive an input signal. The input signal is configured to indicate whether the output stage circuit is to provide dominant or recessive states. The CAN transmitter includes a cascode circuit configured to provide output signals on the output stage circuit to provide dominant or recessive states based on the input signal. The CAN transmitter includes a switch circuit configured to, based upon the input signal, switch the cascode circuit on and off.

Abstract: A system for network data transactions, the system including an ingress port to receive data frames and timestamp received data frames, a frame analyzer to forward the data frames to a processor, the processor to extract timing information from the data frames and update the data frames based on updated timing calculations and output updated data frames via one or more egress ports. Data frames are timestamped at ingress and egress ports, and egress timestamps are saved in a timestamp memory. The system reduces overall network delays by using dedicated hardware and stored timestamp information.

Abstract: An integrated resistor includes a resistor tub, a resistive element, and a dielectric liner. The resistor tub is formed from a conformal metal, and includes a laterally-extending tub base and vertically-extending tub sidewalls extending upwardly from the laterally-extending tub base, wherein the laterally-extending tub base and vertically-extending tub sidewalls define in a resistor tub interior opening. The dielectric liner is formed in the resistor tub interior opening. The resistive element is formed over the dielectric liner in the resistor tub interior opening, and includes a pair of resistor heads connected by a laterally-extending resistor body. The dielectric liner electrically insulates the resistive element from the resistor tub.

Abstract: A device includes a PWM circuit to generate a complementary PWM signal comprised of a positive polarity PWM signal and a negative polarity PWM signal. The positive polarity signal may drive a high-side switch. A trigger multiplexer may take as input the negative polarity PWM signal and may force an output based on a predetermined condition, the predetermined condition including but not limited to the maximum on-time of a low-side switch. The output of the trigger multiplexer may drive a low-side switch. The high-side switch and the low-side switch may drive a load.

Abstract: Teachings of the present disclosure include systems and/or methods for encoding digital data into a handwritten sample. An example method includes: accessing a predetermined vibration pattern stored in a memory corresponding to defined data; and vibrating a stylus based on the predetermined vibration pattern during creation of the handwritten sample to encode the defined data into the handwriting sample.

Abstract: A method of forming a partially silicided element is provided. A silicided structure including a silicide layer on a base structure is formed. A dielectric region is formed over the silicided structure. The dielectric region is etched to form a contact opening exposing a first area of the silicide layer and a tub opening exposing a second area of the silicide layer. A conformal metal is deposited to (a) fill the contact opening to define a contact and (b) form a cup-shaped metal structure in the tub opening. Another etch is performed to remove the cup-shaped metal structure in the tub opening, to remove the underlying silicide layer second area and to expose an underlying area of the base structure, wherein the silicide layer first area remains intact. The base structure with the intact silicide layer first area and removed silicide layer second area defines the partially silicided element.

Abstract: A device for control of network traffic may include a plurality of edge interface circuit and internal interface circuits each coupled to one or more network components. The device may prepend frame identification information to received data frames and remove duplicate data frames when identification information is detected multiple times. The device may store frame identification information in a non-transitory memory device and perform a lookup operation to identify duplicate data frames and eliminate loops in the network.

Abstract: One or more examples relate, generally, to a programmable voltage lockout circuit provided at an electronic device. Such a programmable voltage lockout circuit asserts a lockout of the electronic device at least partially responsive to a user-programmed threshold and a supply voltage of the electronic device. One or more examples relate, generally, to configuring a programmable voltage lockout circuit utilizing a user-programmed threshold.

Abstract: A UART includes a transmission register, a receive register, a virtual remappable pin, a parity error check circuit to evaluate contents of the receive register for a parity error, and control logic to determine contents of the transmission register. The contents include underlying data and a parity bit based thereupon. The control logic is to route the contents through the first virtual remappable pin to the receive register. The control logic is to, before reception of the entire contents at the receive register, cause modified contents to be provided to the receive register. The modified contents are to cause a parity error. The modified contents are to include different underlying data or a different parity bit than the contents of the transmission register. The control logic is to determine whether the parity error check circuit detected the parity error.