Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.

Abstract: An apparatus and method which sequentially selects subsets of data bits read in parallel from an array of memory cells (each cell being operated as a multistate memory device) and sequentially asserts the selected subsets to a data bus. Preferably, the cells are flash memory cells. Preferably, the apparatus includes a sense amplifier circuit, a multiplexer, and circuitry operable to read a number (N) of the cells in parallel, whether the cells are operated as binary or multistate devices. The sense amplifier has N input lines and MN output lines, where M is the number of binary bits in a binary representation of the data read from each cell operated as a multistate device. The multiplexer has MN inputs (each connected to one of the output lines of the sense amplifier circuit), N outputs connected to a data bus having N-bit width, and is controllable to output selected N-bit subsets of the MN bits received at its MN inputs.

Abstract: An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns.

Abstract: A test mode circuit for use in a data system includes a test mode code latch for receiving a test mode code. A switch, which when turned on, couples the test mode code latch to the input so that the test mode code can be transferred from the input to the test mode code latch. A test mode command decoder is coupled to the test mode code latch for decoding the test mode code to initiate a test mode of operation in the data system. A data storage unit is coupled to the test mode command decoder for storing a data bit which corresponds to a low voltage test mode enable signal. The data bit may be modified during the test mode of operation. A low voltage test mode circuit is coupled to the data storage unit which, after first being enabled by the low voltage test mode enable signal, can be controlled to turn the switch on and off. An enable signal generation circuit couples the low voltage test mode circuit to the switch for turning the switch on and off.

Abstract: An apparatus determining the state of a multistate memory cell. The apparatus includes three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. The apparatus includes circuitry which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell.

Abstract: An integrated memory circuit having an array of memory cells and which is operable in at least one test mode as well as in a normal operating mode, and a true V.sub.th measurement test implemented by such circuit The memory circuit includes circuitry for implementing a true V.sub.th measurement test mode in which an external voltage (or a sequence of external voltages) is applied to an external pad, and a test voltage at least substantially equal to such external voltage (or a sequence of test voltages, each at least substantially equal to one of a sequence of external voltages) is applied directly to the control gates of all or selected ones of rows of the cells (e.g., to all or selected ones of the wordlines of the array). In preferred embodiments, each memory cell is a nonvolatile memory cell such as a flash memory cell.

Abstract: A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with each of the cells including a source region, a drain region, a channel region intermediate the drain and source region, a floating gate disposed over the channel region and a control gate disposed over the floating gate, with the cells located in one of the array columns having their drains connected to a common bit line and with the cells in one of the rows having their control gates connected to a common word line. The memory system includes a control circuit carrying out read, programming and erase operations. The erase operation is performed by applying a negative voltage to control gate of the cell being erased and a positive voltage to the source of the cells being erased.

Abstract: An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.

Abstract: An apparatus and method for programming the memory cells of a multistate memory. The method involves the collapsing of data before transmitting to the memory cells. A controller generates optimized program pulses of high voltage to apply to the memory cells. The pulses vary in amplitude and time, depending on the state level being transitioned. Program verify is performed by reading the programmed data back into the controller where it is compared with the original value intended for programming. This compare operation modifies the data read and initial data to reflect which memory cells require further programming. The modified data is again collapsed and sent to the memory for further programming and verify cycles until a monitoring circuit within the controller detects that no further programming is required.

Abstract: A level detection circuit for monitoring the level of a power supply voltage and producing an output signal at power on for resetting various system elements powered by the supply voltage when the supply voltage reaches a predetermined level. The detection circuit, which is powered by the supply voltage includes a voltage reference circuit which produces a reference voltage having a magnitude which is relatively independent of the power supply voltage. A translator circuit functions to produce a translated voltage indicative of the supply voltage magnitude and which is comparable in magnitude to the reference voltage when the supply voltage is at a suitable level such that the system will accept a power on reset pulse. A comparator circuit functions to compare the reference voltage with the translated voltage and cause an associated output circuit to issue the reset pulse. The reset circuit typically includes a one shot circuit, the output of which is logically ORed with the amplified comparator output.

Abstract: A method for detecting an under-programming or over-programming condition in a multistate memory cell. The method uses three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. Control circuitry is used which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell. This information is used by a controller to determine if a memory cell has been over-programmed, under-programmed, or properly programmed. If the cell has not been properly programmed, then additional programming pulses are applied (in the case of under-programming) or an error flag is set and the programming algorithm is terminated (in the case of an over-programmed cell).

Abstract: A data input/output circuit used to program the cells of a memory array or to determine the state of those cells. The circuit includes a data write path used for programming the memory cells in the array and a data read path for reading data indicative of the state of the cells. The data write path includes switching means for electrically disconnecting the high capacitance elements of the write path from the read path. The switching means is under the control of a control means which acts to enable or disable the switching means. The switching means serves to electrically isolate the high capacitance elements of the write path from the read path, thereby increasing the speed with which a read operation be performed.

Abstract: An oscillator circuit capable of being fully implemented in integrated circuit form and having a first current source for charging a first capacitor so as to produce a time varying voltage which is sensed by a first comparator when the voltage reaches a predetermined threshold level. The circuit further includes a second current source for charging a second capacitor so as to produce a further time varying voltage which is sensed by a second comparator when the voltage reaches the predetermined threshold voltage. The output of first and second comparators are combined so as to produce the output clock signal, with the first cycle segment of the clock having a duration determined by the first comparator output and the second cycle segment of the clock having a duration determined by the second comparator output.

Abstract: A data input/output circuit used to program the cells of a memory array or to determine the state of those cells. The circuit includes a data write path used for programming the memory cells in the array and a data read path for reading data indicative of the state of the cells. The data write path includes switching means for electrically disconnecting the high capacitance elements of the write path from the read path. The switching means is under the control of a control means which acts to enable or disable the switching means. The switching means serves to electrically isolate the high capacitance elements of the write path from the read path, thereby increasing the speed with which a read operation be performed.

Abstract: A fast-sensing amplifier for a flash memory comprised of a plurality of floating-gate memory devices and having a column line selectively coupled to the devices is disclosed. The column line is quickly discharged to ground before a read-biasing and amplifying circuit quickly pulls up the line to the read-bias potential at a particular memory device. This potential is compared to a sense-reference potential by a differential amplifier within the fast-sensing amplifier. The binary state of the particular memory device is provided as the output of the fast-sensing amplifier.

Abstract: A nonvolatile memory system emulates a magnetic hard disk drive and includes an array of nonvolatile memory cells, such as flash memory cells, organized into sets, such as sectors. A buffer, such as a random access memory, stores a first set of data to be written to the array. Error correction code (ECC) circuitry receives the first set of data and calculates first ECC check bits representative of the first set of data. ECC comparison circuitry compares the first ECC check bits with second ECC check bits representative of a second set of data stored in the array to generate an ECC comparison signal having a first state indicative of a match between the first and second ECC check bits and a second state indicative of a miscomparison between the first and second ECC check bits.

Abstract: A flash memory system having the capability of automatically executing consecutive program-erase cycles for the purpose of measuring the endurance of the memory. The memory system may be switched to a test mode which triggers the autocycling by applying a high voltage to two of the package pins of the system which normally are coupled to low voltage sources. The system includes an internal state machine which, in normal operation, is implemented to perform flash cell programming, erasing and reading, with the erasing sequence including a preprogram step where, prior to the erase, all cells are programmed. When placed in the autocycle mode by application of the high voltages to the pins, the state machine is caused to enter the erase sequence, including the preprogram step. Once the first erase sequence is concluded, circuitry is provided that causes the state machine to automatically initiate a further erase sequence.

Abstract: A controllable one-shot circuit for use in a control unit of a memory circuit, for asserting a control signal with variable (and controllable) duration in response to a trigger signal, and a state machine for controlling memory operations of a memory circuit which includes such a controllable one-shot circuit. In preferred embodiments, the one-shot and the state machine of which it is a part are implemented as parts of a single memory chip (preferably, a nonvolatile memory chip such as an integrated flash memory circuit). Other aspects of the invention are methods of operating a state machine of a memory circuit to generate control signals for use in controlling memory operations performed by the memory circuit.

Abstract: A high voltage detection circuit implemented in an integrated circuit which is switchable between a normal operation mode and an alternative operation mode and having contact pads for electrically connecting the integrated circuit to an external environment. One of the pads functions to provide an interface between an external environment and the integrated circuit for signals having a maximum voltage magnitude, relative to a circuit common, when the integrated circuit is in the normal operation mode. The one pad further functions to receive an external test mode signal which will cause the integrated circuit to switch to the test mode of operation, with the test mode signal having a voltage magnitude which is greater than that of maximum voltage magnitude. The detection circuit includes a first MOS transistor having either the gate or source coupled to the one pad and a second MOS transistor having a source and drain connected in series with the drain and source of the first transistor.

Abstract: First and second flash memory cells or transistors, operating in the linear region of operation, are provided with different threshold values by providing different charges on their respective floating gates. The first of the pair of flash memory transistors is "over-erased" until it has a negative threshold voltage so that the first flash memory transistor is rendered permanently conducting when its control gate and source are at V.sub.ss. Circuitry is provided for connecting the first and second flash memory transistors in parallel circuits in which equal current values are generated in an equilibrium condition. Circuitry for sensing a voltage in each of the parallel circuits is provided to determine any imbalance in current values and provide an output voltage which may be used as an reference value when the currents are in equilibrium.