Abstract: A memory circuit including at least one of flash memory calls organized into one or more physically separate decode blocks and a controller which monitors the disturb effect on each independently erasable "erase" block of cells of each decode block due to erasures of other erase blocks in the same decode block, and a method of operating such a circuit. Preferably, the controller controls memory operations of each array in addition to monitoring the disturb effect on each erase block. The disturb effect causes cells of an erase block to lose charge from their floating gates each time an erase operation is performed on another erase block in the same decode block. Preferably, each time an erase block is erased, the controller updates a table for the decode block which contains the erased block by adding a unit of disturb to the count for each other erase block in the decode block and resetting the count for the erased block to zero.

Abstract: An integrated circuit operable in a test mode and a normal operating mode, which includes an improved test mode switch. In the test mode of preferred embodiments in which the circuit is an integrated memory chip, the test mode switch is closed so as to connect an input/output (I/O) pad directly with a selected memory cell (so a current/voltage characterization of the cell can be obtained). In the normal operating mode of these embodiments, the test mode switch is open and it isolates the I/O pad from direct connection with the selected cell even under the condition that a transistor of the test mode switch undesirably becomes conductive (e.g., due to low voltage on the I/O pad, inductive coupling, or the like).

Abstract: An operational amplifier-based voltage multiplier circuit ("op amp circuit") implemented as an integrated circuit, and a memory chip including such an op amp circuit. The op amp circuit includes a variable operational feedback or input resistance (or a variable operational feedback resistance and a variable input resistance), and preferably also circuitry for controlling at least one variable resistance in response to control bits to cause the op amp circuit to assert a selected output voltage in response to a given input voltage. Preferably, each set of control bits determines a binary control word whose binary value has a simple functional relation to the value of the output voltage selected thereby. Preferably, the memory chip includes an array of memory cells (e.g, flash memory cells) and a control unit for controlling memory operations including programming, reading, and erasing the memory cells.

Abstract: A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.

Abstract: An address transition detection (ATD) circuit for use in a memory generates a first pulse in a first node in response to a change in state of an address signal and generates a second pulse in a second node in response to a change in state of the address signal. A load circuit accelerates assertion of the first pulse in response to assertion of the second pulse and accelerates deassertion of the first pulse in response to deassertion of the second pulse.

Abstract: A non-volatile data storage unit having a data input and a volatile memory device for storing data. The volatile memory device is preferably a latch circuit made up of a pair of cross-coupled inverter circuits which store the data in complementary form. A non-volatile memory device, such as a pair of flash memory cells, is included which also store data in complementary form. Control circuitry is provided for controlling the operation of the data storage unit, including circuitry for transferring data from the data input to the volatile memory device and circuitry for programming the non-volatile memory device with data from the volatile memory device. The storage unit also preferably includes circuitry for transferring data stored in the non-volatile memory device to the volatile memory device, with such transfer typically taking place after an interruption of power to the storage unit.

Abstract: A filtered command port architecture for a memory array is disclosed. A command controller is directly connected to the memory array and receives command instructions from an external microprocessor via an address and data bus. A command clock is used to latch commands from the data bus into a command decoder. A timing signal is used to filter incoming signals from the data bus which are asserted for less than a predetermined amount of time. A state decoder then tracks a sequence of commands from the command decoder and performs an appropriate action in response to the commands.

Abstract: A circuit which responds to an external standby command (a transition in a chip enable signal from an external device) by generating a delayed internal standby signal. The internal standby signal functions by switching selected components of the circuit (such as address buffers) from an active mode to a standby mode. In preferred embodiments, the circuit is a memory circuit implemented as an integrated circuit. The amount of the delay in generating the delayed internal standby signal is selected to achieve a desired decreased average response time to a sequence of commands (such as memory access commands) without excessive power consumption. In embodiments in which the circuit is a memory chip (such as a flash memory chip) having address access time in the range from 60 ns to 80 ns, the delay typically is from about 100 ns to about 200 ns.

Abstract: A method for verifying the status of selected nonvolatile memory cells of an integrated memory circuit, such as during a memory erase or programming operation, and an integrated nonvolatile memory circuit including circuitry for performing this verification method. Preferably, the invention employs simple logic circuitry including a flip-flop to assert successful verification data only in response to a continuous validity of a verification signal throughout a sampling period, thereby avoiding false assertion of successful verification data. The sampling period is preferably longer than the expected duration of fluctuations due to noise in the verification signal. During the sampling period of a verification operation, the logic circuitry receives a raw verification signal indicative of the instantaneous relation between a measured threshold voltage of a selected memory cell and a reference voltage.

Abstract: A memory system (preferably implemented as an integrated circuit) including an array of memory cells, a control unit for controlling operations of the system (such as programming, reading, and erasing the cells), at least one data storage unit which stores control parameter data determining at least one control parameter for the system, and default parameter circuitry for asserting at desired times one or both of: default control parameter data (regardless of the control parameter data stored in each data storage unit); and at least one default voltage level (in place of an otherwise asserted voltage level). In preferred embodiments, the default control parameter data (or voltage levels) are asserted during a test initialize mode in response to an initialization signal generated by the control unit, for use in initializing internal control registers (and voltage levels) of the system so that an external program for controlling the system during the test mode can start from a known condition.

Abstract: A memory system including means for verifying the contents of a memory cell contained in a memory array to determine if a shift in the threshold voltage level has occurred. The memory system is placed into a test mode of operation in which an internal program or erase verify operation is executed under the control of the system's internal state machine. Once in the mode, the memory system steps through each memory cell, address by address, and reads the contents of the cell using the appropriate reference voltage for a programming or erase operation. A status register bit is set indicating successful completion of the verification operation for a block of memory cells. A register bit is also set if a cell fails the verification operation. This provides a more accurate determination of the state of a memory cell than can be achieved by performing an external read operation using read operation or data verification reference voltage levels.

Abstract: A flash memory array arrangement having a plurality of erase blocks which can be separately erased, preferably using negative gate erase techniques. The memory cells are arranged in each erase block to form an array of cell rows and cell columns, with the sources of the cells in each erase block connected to a common source line so as to permit separate erasure. Cells located in row have their control gates connected to a common word line and cells located in one of the columns having their drains connected to a common bit line. The cells located in each erase block have their sources connected to a common source line. Word line control circuitry functions to control the state of the word lines in read, program and erase operations. Separate erase transistors are connected to each word line for the purpose of connecting the word lines of a block to be erased to a negative voltage.

Abstract: An integrated circuit selectively operable in either a first mode (consuming low power) or a second mode (consuming relatively high power). The circuit includes MOS transistors and a supply voltage circuit for at least one of the transistors. In both modes, the supply voltage circuit holds the body of each transistor at a fixed voltage (e.g., a voltage V.sub.CC in a range from 5 to 5.5 volts, where each transistor is a PMOS device). In the second mode the supply voltage circuit supplies this fixed voltage to the source of each transistor, but in the first mode it supplies a voltage equal to or slightly offset from the fixed voltage to the source of each transistor. In some embodiments, the supply voltage circuit (in the first mode, after an initial transient state) supplies a first voltage to a well shared by a plurality of PMOS transistors, and a second voltage to the source of each PMOS device.

Abstract: A CMOS buffer circuit having a trip point which is insensitive to variations in temperature, supply voltages and manufacturing processes. The circuit output stage has three series-connected MOS transistors including an N channel pull-down transistor connected between the buffer output and the circuit common, a first P channel pull-up transistor connected to a positive supply voltage and a second P channel pull-up transistor connected between the first P channel transistor and the buffer output. The gates of the first P channel transistor and the N channel transistor are connected together to form the buffer input. An N channel reference transistor is used to generate a reference current which is mirrored into the output stage by a third P channel transistor which is connected to the second P channel transistor of the output stage so as to form a current mirror.

Abstract: A data input/output circuit used to program the cells of a memory array or to determine the state of those cells. The circuit includes a data write path used for programming the memory cells in the array and a data read path for reading data indicative of the state of the cells. The data write path includes switching means for electrically disconnecting the high capacitance elements of the write path from the read path. The switching means is under the control of a control means which acts to enable or disable the switching means. The switching means serves to electrically isolate the high capacitance elements of the write path from the read path, thereby increasing the speed with which a read operation be performed.

Abstract: An integrated memory circuit (chip) and methods for testing the chip. The chip has an array of memory cells, a sense amplifier for reading selected ones of the cells, and a switch having a first state allowing an external device connected to an external pad to sink a reference current from the sense amplifier and a second state disconnecting the pad from the sense amplifier (so that an internally generated reference current can be supplied to the sense amplifier with the switch in the second state). In the first state, the switch preferably is tolerant of a broad and continuous range of voltages on the pad. In some test modes, cells are read using a sense amplifier of the chip while selected voltages are applied to each cell and external equipment sinks reference current flowing from the sense amplifier through an external pad, thus sensing data from each cell with all the timing constraints usually placed on a read of the cell in the normal mode.

Abstract: A memory chip and method for operating a memory chip, in which one or more nodes are monitored to identify an illegal condition, and a halt signal is asserted in response to the illegal condition. If an illegal condition is identified during a high voltage mode in which high voltage is applied across transistors of the chip, assertion of the halt signal is delayed until the end of the high voltage mode. In response to the halt signal, the chip halts an operation such as a memory cell erase operation. By avoiding halt signal assertion during a high voltage mode, the invention avoids problems (e.g., due to the snap back bipolar effect) which could otherwise result due to switching of transistors of the chip during the process of halting chip operation in the high voltage mode.

Abstract: An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns.

Abstract: An apparatus which allows the pulse duration of the high voltage pulses used in the programming and erase operations of a non-volatile memory system to be determined by an external timing signal instead of the internal timer normally used. Control of the pulse duration by the internal timer is disabled by gating the timer output signal with the external signal in a manner such that the gate output signal (which triggers the end of the high voltage pulse) is only generated when the external timing signal has a predetermined value. By controlling the value of the external timing signal, the pulse duration can be varied and have values other than those which would result from use of the internal timer.

Abstract: A flash memory array having a reduced number of metal source lines and increased storage density. The cells are arranged in rows and columns, with the cells in a row having their control gates connected to a common word line and the cells in a column having their drains connected to a common bit line. All of the cell sources of the array are connected together with a combination of doped semiconductor and metal lines. The source metal lines are disposed generally in parallel with the bit lines. In order to reduce the number of source metal lines, the lines are spaced apart by, typically, eight, sixteen or more cell columns. The metal source lines define a sub-array therebetween. The array includes a decoder for accessing two cells in different columns of each sub-array during single reading and programming operations. Thus, each sub-array provides two bits of data rather than the customary one bit.