Abstract: A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

Abstract: A microelectronic device having a stack structure with an alternating sequence of conductive material and insulative material arranged in tiers, and having blocks separated by dielectric slot structures. Each of the blocks has a stadium structure, a filled trench overlying the stadium structure, support structures extending through the filled trench and tiers of the stack structure, and dielectric liner structures covering sidewalls of the support structures. The stadium structure has staircase structures each having steps with edges of the tiers of the stack structure. The filled trench has a dielectric material interposed between at least two additional dielectric materials. The dielectric liner structures have first protrusions at vertical positions of the dielectric material, and second protrusions at vertical positions of the conductive material of the tiers of the stack structure. The second protrusions have greater horizontal dimensions that the first protrusions.

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

Abstract: An indication to perform a write operation at a memory component can be received. A voltage pulse can be applied to a destination block of the memory component to store data of the write operation, the voltage pulse being at a first voltage level associated with a programmed state. An erase operation for the destination block can be performed to change the voltage state of the memory cell from the programmed state to a second voltage state associated with an erased state. A write operation can be performed to write the data to the destination block upon changing the voltage state of the memory cell to the second voltage state.

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

Abstract: Apparatuses, methods, and systems for generating patterns for memory using threshold voltage difference are disclosed. An embodiment includes circuitry and a memory array including a plurality of memory cells. The circuitry can select a group of memory cells from the plurality of memory cells, program each memory cell of the group to a first data state, determine a first threshold voltage of each memory cell of the group, program each memory cell of the group to a second data state, perform a number of snapback events on each memory cell of the group, program each memory cell of the group to the first data state, determine a second threshold voltage of each memory cell of the group having the first data state, and generate a pattern for the memory array based, at least in part, on a difference between the first threshold voltage and the second threshold voltage.

Abstract: Apparatuses, systems, and methods for memory initiated calibration. The memory includes a termination circuit with a tunable resistor and a calibration detection circuit with a replica tunable resistor. The calibration detection circuit measures a resistance of the replica tunable resistor and provides a calibration request signal if the resistance is outside a tolerance. Responsive to the calibration request signal, a controller of the memory schedules the memory for a calibration operation.

Abstract: Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.

Abstract: An apparatus that includes a semiconductor substrate having first and second gate trenches arranged in parallel and extending in a first direction, and first and second gate electrodes embedded in the first and second gate trenches, respectively, via a gate insulating film. Each of the first and second gate electrodes includes a first conductive film located at a bottom of the respective first and second gate trenches and a second conductive film stacked on the first conductive film. The second conductive film included in a first portion of the second gate electrode is thinner than the second conductive film included in a first portion of the first gate electrode which is arranged adjacently to the first portion of the second gate electrode in a second direction crossing to the first direction. The second conductive film is lower in work function than the first conductive film.

Abstract: An apparatus that includes a first conductive pattern positioned at a first wiring layer and extending in a first direction, a second conductive pattern positioned at a second wiring layer located above the first wiring layer and extending in a second direction, and a contact plug connecting the first conductive pattern with the second conductive pattern. The contact plug includes a lower conductive section contacting the first conductive pattern and an upper conductive section contacting the second conductive pattern. The width of the lower conductive section on a first boundary between the lower and upper conductive sections in the first direction is greater than the width of the upper conductive section on the first boundary in the first direction and the width of the second conductive pattern on a second boundary between the contact plug and the second conductive pattern in the first direction.

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material in a lowest of the conductive tiers comprises intervenor material. Bridges extend laterally-between the immediately-laterally-adjacent memory blocks. The bridges comprise bridging material that is of different composition from that of the intervenor material. The bridges are longitudinally-spaced-along the immediately-laterally-adjacent memory blocks by the intervenor material and extend laterally into the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

Abstract: Methods, systems, and devices for row address latching for multiple activate command protocol are described. A memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. The memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. The memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate message probability compute data based on encoded data (e.g., data encoded using one or more encoding techniques). The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate message probability compute data for a message probability compute (MPC) decoder. In this manner, neural networks or recurrent neural networks described herein may be used to implement aspects of error correction coding (ECC) decoders, e.g., an MPC decoder that iteratively decodes encoded data.

Abstract: Methods and apparatuses associated with surface cleaning are described. Examples can include detecting at a processing resource of a robot and via a temperature sensor of the robot, a temperature of a surface on which the robot is located. Examples can include the processing resource shutting down the robot in response to the temperature being at or above a particular threshold temperature, and the processing resource instructing the robot to clean the surface following a particular cleaning path using a vacuum, a scrubber, or both in response to the temperature being below a particular threshold temperature.

Abstract: A method includes determining that a ratio of valid data portions of a block of memory cells is greater than or less than a valid data portion threshold and performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions is greater than the valid data portion threshold. The method further includes performing a second media management operation on the block of memory cells in response to determining that the ratio of valid data portions is less than the valid data portion threshold.

Abstract: Disclosed herein is an apparatus that includes a clock generator configured to generate first to fourth clock signals based on an input clock signal, a first duty-cycle detector configured to output a first signal responsive to a comparison between information produced based on the first and second clock signals and based on the third and fourth clock signals, a second duty-cycle detector configured to output a second signal responsive to a comparison between information produced based on the first and fourth clock signals and based on the second and third clock signals, a third duty-cycle detector configured to output a third signal responsive to a comparison between information produced based on the first and third clock signals and based on the second and fourth clock signals, and a duty-cycle adjuster configured to adjust a duty-cycle of the input clock signal responsive to the first to third signals.

Abstract: A method includes receiving a request for an allocation of memory resources based on quality of service (QoS) parameters. The method further includes provisioning, via a QoS manager component, a plurality of physical functions to provide the requested allocation of resources. At least two of the plurality of physical functions can be provided to meet a QoS criteria.

Abstract: Methods, systems, and devices for opportunistic data movement are described. A memory device may include a non-volatile memory and a volatile memory that operates as a cache for the non-volatile memory. The memory device may receive a write command from a host device. The write command may be associated with a row of a bank in a volatile memory. The memory device may write data associated with the write command to a buffer that is associated with the bank and that is coupled with the volatile memory. And the memory device may communicate the data from the buffer to the volatile memory based on the write command and before a pre-charge command for the row of the bank is received from the host device.

Abstract: An input/output (I/O) command referencing a memory device is identified. A power limit of the memory device is determined. A power level associated with executing the I/O command is estimated. Responsive to determining that the power level satisfies the power limit, the I/O command is executed.