Abstract: A method for generating a secure nonce using a one-time programmable (OTP) memory within an integrated circuit to provide persistence, the method including randomly selecting k currently-unprogrammed bits in the OTP memory, creating a data set using data derived from current contents of the OTP memory altered by changing the states of the k currently-unprogrammed bits of the OTP memory, and employing as the secure nonce the data set or data derived from the data set. The selected k bits are programmed in the OTP memory.

Abstract: A method for automatically refreshing a non-volatile memory array in the background without memory interruption includes selecting an unrefreshed segment of the memory, reading data from each row in the selected segment during memory dead time and storing the data read from each row in a local temporary storage memory until an entire segment is read out, remapping all memory addresses in the selected segment to the temporary storage memory, isolating column lines in the selected segment from global column lines, erasing the data in the selected segment without disturbing the column lines, rewriting memory data in each row of the selected segment, remapping all memory addresses in the selected segment to the memory, and repeating the process until all segments have been refreshed.

Abstract: A circuit internal to a programmable integrated circuit for preventing laser interrogation of the programmable integrated circuit includes a sense resistor connected between a deep n-well and a source of bias voltage for the deep n-well. A voltage-sensing circuit is coupled across the sense resistor to measure voltage across the sense resistor. A tamper trigger circuit responsive to the voltage sensing circuit generates a tamper signal in response to a voltage sensed in the voltage sensing circuit having a magnitude greater than a threshold value.

Abstract: A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel. In at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extends from the drain into the channel.

Abstract: An integrated circuit is formed on a p-type semiconductor substrate connected to ground potential. A deep n-well is disposed in the p-type substrate. A p-well is disposed in the deep n-well. An n+ drain region and an n+ source region are disposed in the p-well, the n+ source region connected to a common potential. A p-type contact is disposed in the p-well and is connected to ground potential through a resistor.

Abstract: A method for implementing an instant boot function in a customizable system on a chip (SoC) integrated circuit having an application specific integrated circuit portion including configuration registers includes providing a field programmable gate array fabric on the SoC, providing non-volatile memory cells on the SoC, and initializing the configuration registers using data from the non-volatile memory cells during a system reset mode of operation of the integrated circuit.

Abstract: A circuit internal to a programmable integrated circuit for preventing laser interrogation of the programmable integrated circuit includes a sense resistor connected between a deep n-well and a source of bias voltage for the deep n-well. A voltage-sensing circuit is coupled across the sense resistor to measure voltage across the sense resistor. A tamper trigger circuit responsive to the voltage sensing circuit generates a tamper signal in response to a voltage sensed in the voltage sensing circuit having a magnitude greater than a threshold value.

Abstract: A method for determining if an individual integrated circuit was manufactured using an individual instance of tooling includes collecting from the individual integrated circuit first data representing at least one attribute that varies as a function of the tooling used to manufacture the individual integrated circuit and second data identifying the integrated circuit as having been manufactured using the individual instance of tooling. The first data is compared to a signature of the individual instance of tooling identified by the second data. The signature is derived from the at least one attribute measured from a population of integrated circuits that were manufactured using the individual instance of tooling. The individual integrated circuit is identified as having been manufactured using the individual instance of tooling identified in the second data collected from the individual integrated circuit if the first data correlates to the signature by a predetermined threshold.

Abstract: A gate-boosting transmission gate includes an input node and an output node. An n-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold. A p-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold.

Abstract: An integrated circuit is formed on a p-type semiconductor substrate connected to ground potential. A deep n-well is disposed in the p-type substrate. A p-well is disposed in the deep n-well. An n+ drain region and an n+ source region are disposed in the p-well, the n+ source region connected to a common potential. A p-type contact is disposed in the p-well and is connected to ground potential through a resistor.

Abstract: A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.

Abstract: A method for performing auto-refresh of a SONOS memory in a field programmable gate array in a system, includes sensing an auto-refresh condition, selecting a memory segment that has not yet been refreshed, storing the contents of memory segment, erasing the memory cells in the memory segment, and reprogramming the memory cells in the memory segment, until all of the memory segments have been reprogrammed.

Abstract: A layout arrangement for a resistive random access memory cell includes an active area, a polysilicon row address line over the active region, a metal column address line running orthogonal to the row address line and having an active region contact portion extending over the active region and having a contact to the active region. A metal output line runs parallel to the column address line over the active region. A first cell contact region intersects with the output line and has a contact to the active region. A first metal cell contact region forms an intersection with the first cell contact region. A first resistive random access memory device is formed at the intersection of the first cell contact region and the output line. A second resistive random access memory device is formed at the intersection of the first cell contact region and the first cell contact region.

Abstract: A method for programming a cluster-based field programmable gate array (FPGA) device includes providing a netlist and cluster size information, translating the netlist into a hypergraph, partitioning the hypergraph into multiple partitions and optimizing the Rent characteristic, translating the partitions into clusters, placing the clusters on the FPGA device, routing interconnects using a pre-fabricated routing resource on the FPGA device, generating a programming bitstream in response to the placing and routing, and providing the programming bitstream to the FPGA device to realize the user design.

Abstract: A method for controlling the use of intellectual property (IP) in an individual integrated circuit includes loading data including the IP into the individual integrated circuit, loading an IP license certificate into the individual integrated circuit, the certificate including identification of the IP authorized for the individual integrated circuit, determining inside the individual integrated circuit whether the IP is authorized for the individual integrated circuit, enabling operation of the individual integrated circuit if the IP circuit is authorized for use in the individual integrated circuit, and imposing a penalty on operation of the individual integrated circuit if the IP is not authorized for use in the individual integrated circuit.

Abstract: A method for controlling the use of intellectual property (IP) in an individual integrated circuit includes loading data including the IP into the individual integrated circuit, loading an IP license certificate into the individual integrated circuit, the certificate including identification of the IP authorized for the individual integrated circuit, determining inside the individual integrated circuit whether the IP is authorized for the individual integrated circuit, enabling operation of the individual integrated circuit if the IP circuit is authorized for use in the individual integrated circuit, and imposing a penalty on operation of the individual integrated circuit if the IP is not authorized for use in the individual integrated circuit.

Abstract: An integrated programmable logic circuit having a read/write probe includes a plurality of programmable logic circuits having internal circuit nodes and a plurality of flip flops, each having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node, a probe-data line, an address circuit for selecting one of the internal circuit nodes, a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line, a data input path to the asynchronous data input line of each flip flop, a write-probe data input path to the asynchronous data input line of each flip flop, a write-probe enable line, and selection circuitry, responsive to the address circuit and the write-probe enable line, to couple one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.

Abstract: A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, which includes detecting tampering with the FPGA, disconnecting power from the programmable logic core, and simultaneously programming the n-channel device and erasing the p-channel device in all cells.

Abstract: A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. A body contact is disposed in the p-type isolation ring.

Abstract: A high-voltage transistor includes an active region including a diffused region of a first conductivity type defined by inner edges of a border of shallow trench isolation. A gate having side edges and end edges is disposed over the active region. Spaced apart source and drain regions of a second conductivity type opposite the first conductivity type are disposed in the active region outwardly with respect to the side edges of the gate. Lightly-doped regions of the second conductivity type more lightly-doped than the source and drain regions surround the source and drain regions and extend inwardly between the source and drain regions towards the gate to define a channel, and outwardly towards all of the inner edges of the shallow trench isolation. Outer edges of the lightly-doped region from at least the drain region are spaced apart from the inner edges of the shallow trench isolation.