Abstract: An integrated circuit includes a clock input, a first output, and a second output. A programmable pulse generator has a programmable pulse counter coupled to the clock input at least one control input for receiving count information. A fixed delay element is coupled to the programmable pulse counter. A programmable delay element is coupled to the programmable pulse counter and has at least one control input for receiving delay information. A first multiplexer is coupled to the fixed delay element, the programmable delay element and to the first output. A second multiplexer is coupled to the programmable delay element, the output of the fixed delay element and the second output.

Abstract: An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.

Abstract: A resistive random access memory cell formed in an integrated circuit includes first and second resistive random access memory devices, each including an anode and a cathode. The anode of the second resistive random access memory device is connected to the anode of the first resistive random access memory device. A programming transistor has a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anodes of the first and second resistive random access memory devices, and a gate connected to a program-enable node.

Abstract: A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.

Abstract: A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. A body contact is disposed in the p-type isolation ring.

Abstract: A method for performing on-chip spatial debugging of a user circuit programmed into a user-programmable integrated circuit includes halting an internal clock driving synchronous logic elements in the integrated circuit and reading the states of all synchronous logic elements programmed into the integrated circuit while the internal clock is halted. An interrupt to an embedded processor in the integrated circuit running a user application can also be generated. The output of at least one synchronous logic element can be forced to a desired state while the internal clock is halted. The clock can then be restarted or stepped.

Abstract: A method for automatically refreshing a non-volatile memory array in the background without memory interruption includes selecting an unrefreshed segment of the memory, reading data from each row in the selected segment during memory dead time and storing the data read from each row in a local temporary storage memory until an entire segment is read out, remapping all memory addresses in the selected segment to the temporary storage memory, isolating column lines in the selected segment from global column lines, erasing the data in the selected segment without disturbing the column lines, rewriting memory data in each row of the selected segment, remapping all memory addresses in the selected segment to the memory, and repeating the process until all segments have been refreshed.

Abstract: A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel. In at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extends from the drain into the channel.

Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.

Abstract: A tamper-resistant bus architecture for secure lock bit transfer in an integrated circuit includes a nonvolatile memory having an n-bit storage region for storing encoded lock bits, A plurality of read access circuits are coupled to the nonvolatile memory. An n-bit tamper-resistant bus is coupled to the read access circuits. A decoder is coupled to the tamper-resistant bus. A k-bit decoded lock signal bus is coupled to the decoder. A controller is coupled to the k-bit decoded lock signal bus.

Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

Abstract: A resistive random access memory cell formed in an integrated circuit includes a first resistive random access memory device including an anode and a cathode, a second resistive random access memory device including an anode and a cathode, the cathode of the second resistive random access memory device connected to the anode of the first resistive random access memory device, a programming transistor having a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device, and a gate connected to a program-enable nod, and at least one switch transistor having a gate connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device.

Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.