Abstract: A method and system for encoding ancillary information at a transmitter in a high-speed communications network, the method comprising: generating an electromagnetic interference (EMI) reduction signal; receiving an ancillary data symbol; generating an EMI reduction signal variation based on the ancillary data symbol; and varying a characteristic of the EMI reduction signal based on the generated EMI reduction signal variation to encode the ancillary data symbol in the varied EMI reduction signal.

Abstract: A method and apparatus for modulating a beam from a laser with an electro-absorption modulator, and determining the optical power of the beam by measuring a back current produced by the electro-absorption modulator. The apparatus comprises an electro-absorption modulator and a back current detector. The electro-absorption modulator receives an electronic digital signal from an electro-absorption driver. The electro-absorption modulator modulates the beam of the laser according to the electronic digital signal. While modulating the beam, the electro-absorption modulator produces a back current. This back current is proportional to the optical power of the beam. The back current detector measures the back current to determine the optical power of the beam.

Abstract: The present disclosure provides a means to adjust the relative location of output rising and falling transitions to reduce single-ended duty cycle distortion (DCD) effects in the output data stream originating from the transmitter data path. This serves to improve high-speed single-ended signal characteristics and reduce electromagnetic interference (EMI). Another feature enabled by embodiments of the present disclosure is polarity skew (also referred to as differential skew) reduction between transmitter outputs. In an embodiment, the disclosed method and apparatus for transmitter data path single-ended DCD correction describes a closed-loop calibration system including the actuation apparatus within the transmitter, a sensing block at the output of the transmitter to measure the amount of single-ended DCD, and a calibration block operating on the sensor output to devise correction control inputs to the actuator in the transmitter to correct the data path single-ended DCD present.

Abstract: An apparatus for monitoring operation of a design under test (DUT) comprises a plurality of inputs comprising: an incoming clock edge input connected to detect active clock edges provided to a monitored clock gate; an outgoing clock edge input connected to detect active clock edges sent from the monitored clock gate; an enable input connected to detect enable signals provided to the monitored clock gate and any leaf clock gates connected to receive clock edges through the monitored clock gate; and a protocol input connected to receive protocol signals specifying when the monitored clock gate is required to output active clock edges. The apparatus also comprises a memory in communication with the inputs for storing values from the inputs, and a processor in communication with the memory and the inputs, the processor programmed to determine protocol compliance and to calculate energy consequences of dropping of active clock edges.

Abstract: A method and system for allocating memory in a RAID system. A RAID system requires the use of shared memory to store processed data related to operations of different mass storage devices. Certain RAID algorithms require different sizes of memory regions of the memory, and multiple requests to lock the required memory regions are therefore required. As multiple requests are made in parallel for different operations, the multiple requests for each operation are sorted in a predetermined order. This ensures that all memory regions for one operation can be locked. Requests for memory regions locked by a second operation are held in a pending state to wait for release of those memory regions by a first operation, at which point they are locked again by the second operation.

Abstract: A method and apparatus for powering up and powering down a laser diode and its driver are disclosed. The disclosed method and apparatus enable the use of deep sub-micron CMOS technology to build a laser diode driver (LDD), while ensuring the low voltage limits prescribed by such technology are not exceeded. Building an LDD with deep sub-micron CMOS technology pushes circuit integration further ahead, bringing cost of LDDs and required board circuits down.

Abstract: Controller and method for requesting arbitration of a queue. The controller comprises a coalescing engine for determining a number of commands in a queue and requesting arbitration of the queue when a coalescing condition is satisfied. The method comprises determining the number of commands in a queue and requesting arbitration of the queue when a coalescing condition is satisfied.

Abstract: A method for boost floor mitigation during a decoding operation performed by a decoder is disclosed herein. The method includes: monitoring for a floor error condition while performing the decoding operation; if a floor error condition has been detected, then: clearing a feedback delay memory in the decoder; downscaling main memory values in the decoder; applying a gain in low-rank columns; and continuing to perform the decoding operation.

Abstract: A method and apparatus as described herein provide a novel modification to any iterative FEC decoder method that can improve FER performance in the error floor region. Many iterative FEC methods, such as commonly used LDPC decoders, have error floors where the performance of the decoder does not improve below a certain threshold. Error Floors are caused by trapping sets from which traditional methods cannot escape. With Stochastic Floor Mitigation, according to embodiments of the present disclosure, noise is strategically added to the operations occurring during decoding resulting in significantly improved error floor performance.

Abstract: An FEC codeword comprises channel information indicating the reliability of the information contained by the FEC codeword. The channel information can be used to generate an initial error channel estimate. Based on the initial error channel estimate, an FEC decoder can decode the FEC codeword to increase the reliability of the information contained by the FEC codeword. According to the present disclosure, a method and system of decoding comprises: comparing a current codeword to a previous codeword in order to identify bits corrected between the previous and current codewords; revising an error channel estimate based on the identified corrected bits, the revised estimate representing a change in the error channel over time; and decoding the codeword based on the revised error channel estimate.

Abstract: A method for accessing data in a storage area network is provided. The method initiates with receiving a request for a list of targets on the storage area network. All the targets on the storage area network are exposed to the requestor and authentication requiring a password is requested from the requestor to grant access to the targets on the storage are network. Access to the targets is granted if the password is acceptable, and access to the targets is refused if the password is unacceptable.

Abstract: The present disclosure relates to a method for manufacturing one or more optical engine packages, each optical engine package comprising a silicon photonic die. The method includes receiving a substrate comprising a package portion and a cutting area adjacent to the package portion, assembling the optical engine package on the substrate such that an edge-coupled waveguide of the silicon photonic die overlaps a boundary between the cutting area and the package portion, and cutting the optical engine package and the substrate in the cutting area to expose the edge-coupled waveguide for optical coupling thereof to an optical fiber core.

Abstract: The present disclosure relates to a method for manufacturing one or more optical engine packages, each optical engine package comprising a silicon photonic die. The method includes receiving a substrate comprising a package portion and a cutting area adjacent to the package portion, assembling the optical engine package on the substrate such that an edge-coupled waveguide of the silicon photonic die overlaps a boundary between the cutting area and the package portion, and cutting the optical engine package and the substrate in the cutting area to expose the edge-coupled waveguide for optical coupling thereof to an optical fiber core.

Abstract: A method of partitioning a verification test bench, the method comprising: receiving a source code of the verification test bench, the source code comprising reactive components for sending test traffic to a design under test (DUT) and for receiving test traffic from the DUT, the source code further comprising analytic components for verifying the test traffic between the reactive components and the DUT; identifying the analytic components in the source code; compiling the reactive components and the DUT into a first executable test bench that can be run in a regression to generate test traffic between the reactive components and the DUT; and compiling the analytic components into a second executable test bench that can be run separately from the first executable test bench in order to verify the test traffic.

Abstract: A system is provided for balancing voltage of two rechargeable energy storage devices connected in series at a common node. A voltage divider is configured to divide a total voltage across the two devices into first and second reference voltages. First and second circuit elements include, respectively: first and second comparators, first and second P-channel MOSFETs, first and second current limiting resistors, and first and second networks of resistors. The first circuit elements are in electrical communication and configured to actively discharge a first device of the two devices when a difference between a voltage at the common node and the first reference voltage is greater than a first predetermined voltage. The-second circuit elements are in electrical communication and configured to actively charge the first device when a difference between the voltage at the common node and the second reference voltage is less than a second predetermined voltage.

Abstract: A method and system are provided for measuring the propagation time, or one-way delay or latency, of an 8B/10B data stream, such as a CPRI stream, through a network using a transport network protocol, such as OTN. Embodiments of the present disclosure do not modify the CPRI client and are unlimited in the amount of delay that can be measured. At first and second network endpoints, information is gathered related to patterns associated with successive occurrences of a control character in the 8B/10B encoded data stream. This information is sent over a side channel separate from the 8B/10B encoded data stream. The one-way delay is determined based on a difference between the information related to the pattern identified at the first and second network endpoints.

Abstract: The present disclosure provides methods and apparatus for dynamically adjusting the common mode voltage at the LC tank node and/or the power supply voltage of a VCO with an LC resonator in order to force oscillation start-up by temporarily increasing gain. Methods according to certain preferred embodiments may reduce power consumption and/or overcome threshold voltage limitations and/or increase frequency and frequency tuning range during normal (steady-state) operation.

Abstract: A cross-coupled complementary balanced electro-mechanical oscillator and a method for generating balanced oscillations. The oscillator comprises an electro-mechanical resonator connected to an oscillator core. The oscillator core comprises capacitively cross-coupled complementary programmable inverters and a resistor network. The capacitors inhibit the inverters from latching to a non-oscillatory direct-current (DC) state. The resistor network forms a high pass filter with the capacitors to inhibit relaxation oscillations. The inverters are programmable such that their gain can be varied over time to avoid parasitic oscillations. The oscillator may be frequency-tunable. The method comprises starting balanced oscillations in the oscillator with a low gain to inhibit high-frequency parasitic oscillation modes, inhibiting latching to a DC state using a capacitance, and inhibiting relaxation oscillations using a high pass filter, and varying gain over time to improve phase noise performance.

Abstract: A method of enabling transport of symmetric latency-sensitive constant-bit-rate (CBR) client data streams over an optical transport network (OTN) is provided. The method performs, utilizing an OTN wrapping device, an OTN wrapping operation on a received first constant-bit-rate (CBR) client data stream to form a first framed OTN data stream. The method determines a static wrapping delay induced on the first CBR client data stream by the OTN wrapping operation, performs, utilizing the OTN wrapping device, an OTN unwrapping operation on a received second framed OTN data stream to extract a second CBR client data stream from the second framed OTN data stream, determines a static unwrapping delay induced on the second framed OTN data stream by the OTN unwrapping operation, and equalizes the static wrapping and unwrapping delays by adjusting, at the OTN wrapping device, at least one of the static wrapping and unwrapping delays.

Abstract: Forward error correction (FEC) decoders, such as Low Density Parity Check (LDPC) decoders are described. Described FEC decoders minimize the number of internal bits in a layered processor of an LDPC decoder while maintaining high coding gain operation of the LDPC decoder. Minimizing the number of internal bits in a layered processor is achieved by non-linearly companding the soft information into lower precision format while maintaining the dynamic range of the data bits. Described FEC decoders may generate updated soft information having a precision that is equal to the channel precision.