Abstract: A Forward Error Correction (FEC) decoder is provided, for example including a Layered Low Density Parity Check (LDPC) component. In an implementation, power consumption of the LDPC decoder is minimized with minimal to no impact on the error correction performance. This is achieved, in an implementation, by partially or fully eliminating redundant operations in the iterative process.

Abstract: The present disclosure provides a monitoring system for monitoring the operation of an integrated circuit, the monitoring system comprising: a reference circuit comprising a reference signal delay path and an output for outputting a reference signal; a monitoring circuit, the monitoring circuit comprising: a programmable delay line for providing a controllably selectable delay path; and an output for outputting a delayed signal; a comparison circuit, for comparing the reference signal to the delayed signal and determining whether the error has occurred based on the comparison.

Abstract: An apparatus and method for scalable frame alignment in a high data-rate communications system. OTUk/ODUk frame alignment uses serial processing of a match vector, or serial processing of received OTUk/ODUk bytes to reduce the footprint occupied by the processing logic.

Abstract: A method and system are provided for converting wideband analog radio frequency (RF) signals to a digital domain. In an implementation, the system comprises: an amplifier for receiving and amplifying a first wideband analog RF signal comprising one or more first narrowband analog RF signals, each first narrowband analog RF signal occupying a distinct non-overlapping spectral band within a spectrum of the first wideband analog RF signal; N down converter modules; N analog-to-digital converters (ADCs); and a cross-connect for connecting any one of the N down converter modules to one or more of the N ADCs to analog-to-digital convert only the first narrowband analog RF signals occupying the distinct non-overlapping spectral bands. The method and system of the present disclosure track the occupied bandwidth of the narrowband analog RF signals that make up a wideband analog RF signal rather than a total bandwidth of the wideband analog RF signal.

Abstract: An oscillator and method for generating a signal are provided. The oscillator comprises an electro-mechanical resonator and a reconfigurable oscillator driver. The reconfigurable oscillator driver starts the oscillator in single-ended mode to avoid latching and transitions the oscillator to differential mode in such a manner as to sustain oscillations therein. The reconfigurable oscillator driver comprises two back-to-back banks of inverters and an adjustable feedback resistor. In single-ended mode, one bank is disabled and the other bank is enabled. To transition to differential mode and improve the quality of the signal, the number of enabled inverters is equalized in both banks.

Abstract: An oscillator and method for generating a signal are provided. The oscillator comprises an electro-mechanical resonator and a reconfigurable oscillator driver. The reconfigurable oscillator driver starts the oscillator in single-ended mode to avoid latching and transitions the oscillator to differential mode in such a manner as to sustain oscillations therein. The reconfigurable oscillator driver comprises two back-to-back banks of inverters and an adjustable feedback resistor. In single-ended mode, one bank is disabled and the other bank is enabled. To transition to differential mode and improve the quality of the signal, the number of enabled inverters is equalized in both banks.

Abstract: A method and decoder are provided to decode a Low Density Parity Check codeword. An additional check processor performs hard-decision processing functions on the LDPC codeword in order to avoid running unnecessary decoder iterations. The method comprises: receiving the ECC codeword at a memory, the received ECC codeword comprising ECC data bits, ECC parity bits, and error detection code bits; soft-decision decoding the received ECC codeword at a soft-decision decoder, to update the ECC codeword according to ECC parity check equations; hard-decision processing the received ECC codeword at a check processor, while the soft-decision decoder performs the soft-decision decoding, to verify the ECC data bits using the error detection code bits; terminating the soft-decision decoding when the ECC data bits are verified, regardless of whether the updated ECC codeword satisfies all of the ECC parity check equations; and, outputting the decoded ECC codeword from the memory after termination of the decoding.

Abstract: A receiver equalizer that provides improved jitter tolerance relative to common adaptation mechanisms and that also provides inter-symbol interference. Improved jitter tolerance is an important benefit for SERDES receivers as tolerance to Sinusoidal Jitter is an important performance metric specified in most industry standards.

Abstract: An Interleaved Radio Frequency Digital-to-Analog Converter (RF DAC) suitable for use in cellular base stations and optimized to give both a wide RF tuning range and a wide RF bandwidth is disclosed. The RF DAC uses two levels of interleaving, the first providing a direct conversion path from Base Band (BB) to RF, and the second providing a variable interleaving factor through the use of summation to optimize the output bandwidth as a function of the RF center frequency. Digital Interpolation, including an arbitrary sample rate conversion filter, allows the RF DAC to operate from a wide range of possible BB sample rates and the DAC sample rate is a fixed ratio of the RF center frequency. As a result, the spurious outputs from the RF DAC are in known locations that are relatively easy to filter out, minimizing the frequency planning tasks required for a complete RF system design.

Abstract: A cross-coupled complementary balanced voltage-controlled oscillator and a method for operating same. The oscillator comprises an electro-mechanical resonator, and an oscillator core. The oscillator core comprises capacitively cross-coupled complementary inverters and a resistor network. The oscillator may comprise a frequency tuning network having inductors for increasing the tuning range. The capacitance inhibit the inverters from latching to a static direct current state. The resistor network forms a high pass filter with the capacitance to inhibit relaxation oscillations. The method comprises enabling the resistor network to form a high pass filter and starting balanced oscillations in the oscillator, the capacitance of the high pass filter for inhibiting latching, and the high pass filter for inhibiting relaxation oscillations. The method may comprise tuning the frequency by varying the capacitance of the oscillator.

Abstract: A method of remapping allocated memory in a queue based switching element having first and second memory elements each allocated to a first port pair. An unallocated block of memory is identified in the first memory element as a candidate block, and an allocated block of memory is identified in the second memory element as a target block. Block information is copied from the target block to the candidate block, and the candidate block is maintained as unallocated. In response to a determination that read and write pointers are in a suitable position for a remapping operation, the candidate block is allocated and the target block is deallocated so that the second memory element becomes unallocated and available for reallocation to a second port pair.

Abstract: A distributed electrostatic discharge (ESD) protection circuit is provided. At frequencies beyond 10 GHz, the parasitic capacitance of primary ESD protection voltage clamping devices, such as diodes, hampers adequate insertion and return loss, in spite of lumped inductor tuning. An ESD protection circuit according to an embodiment of the present disclosure solves the problem by distributing the diode, or voltage clamping device, capacitance among several sections of an artificial transmission line. A transmission line is provided between a single input pad and the protected circuit, with a plurality of voltage clamping sections being distributed along the transmission line. The power and ground ESD return paths are also distributed to ensure a constant current density in the voltage clamping segments, even for fast charged-device model (CDM) discharge events. By sharing the ESD return paths between differential inputs (or outputs), these return paths have no impact on differential return or insertion loss.

Abstract: A data protection system having a host, a solid-state drive (“SSD”) array comprising at least three non-volatile memory express (“NVMe”) drives, each NVMe drive comprising a buffer, and a peripheral component interconnect express (“PCIe”) data bus interfacing the host and the NVMe drives. The NVMe drives are implemented with commands for implementing a RAID volume in the SSD array, wherein the commands are operable to perform RAID operations at the NVMe drives using the buffers of the NVMe drives.

Abstract: A GFP frame filter is provided to filter GFP frame data based on extracted GFP header data. The header data comprises EXI, PTI, and UPI fields. The header data can also comprise a generic header that can be customized to provide additional GFP frame filtering applications. The GFP frame filter comprises a plurality of programmable filters arranged to process GFP header data in parallel according to various programmable filter configurations. The plurality of programmable filters can be configured to operate in conjunction in a particular sequence.

Abstract: On-chip at-speed eye measurements of digitized signals in data and timing recovery circuits are disclosed. Eye diagrams and jitter measurements are used to evaluate signal quality and bath-tub Bit Error Rate characteristics in baseband communication systems. This disclosure describes a method and apparatus for digitally sampling a received signal at speed to produce an eye diagram of the received signal. This involves adding a small amount of circuitry to the existing prior art systems that use an interpolator for timing recovery and data recovery. In the present disclosure a temporary offset is applied to the interpolation index of the interpolator to obtain interpolated samples between the baud center and baud edge. The eye diagram can be produced from the received digitized and interpolated signal before equalization, or alternatively from the equalized signal.

Abstract: A method and system are provided for reducing mismatch between oscillators in an LC VCO array. In an implementation, a method comprises measuring the mismatch between the driver strengths, by measuring the corresponding oscillation amplitudes, and a mismatch between the resonance frequency of each LC VCO in the array of VCOs, and adjusting each LC VCO to reduce the measured amplitude and frequency mismatches. In an implementation, the measuring and adjusting is performed once to calibrate the array of VCOs. In another implementation, the system measures and adjusts the array of VCOs repeatedly. In another implementation, the LC VCO array has a master VCO and a plurality of slave VCOs connected to the master VCO by slave PLLs to reduce phase noise caused by mismatches.

Abstract: A method and apparatus are provided for reducing aliasing in a direct conversion (or zero-IF) radio receiver having high and low frequency paths. According to an implementation, a non-transitory machine-readable memory stores aliasing correlation response data that associates a measured non-aliased signal in a high frequency path and a measured aliased residual of the signal in a low frequency path. A compensator is in communication with the memory to apply aliasing compensation to received signals based on the stored aliasing correlation response data. In an example implementation, the low and high frequency paths are independently optimized for low and high frequency performance, respectively, and have transfer functions that overlap with one another to create a calibration zone used to calibrate the first and second transfer functions.

Abstract: This disclosure provides methods and apparatus for processing differential signals having non-inverted and inverted signals. An example apparatus has first and second circuit arms, each arm connected to receive one of the input signals. Each arm has a main signal path for carrying the respective input signal, and a secondary signal path for carrying a voltage divided and low-pass filtered version of the respective input signal. The outputs of the main and secondary signal paths are combined to produce equalized output signals.

Abstract: A hybrid analog-digital, dual path, delta-sigma modulator (DSM) based fractional-N phase-lock-loop (PLL) that includes an integral path and a proportional path is provided. The integral path is implemented in the digital domain. The proportional path may be implemented in either the digital or analog domain. A feed-forward error correction signal generator is used to generate a feed-forward signal for attenuating in-band spurs generated by the quantization error of the integral path phase detector.

Abstract: A frame delineation method for a generic framing procedure (GFP) that includes: searching a serial data stream comprising GFP frames, octet by octet, to identify an eight octet sequence; and delineating GFP frames from the serial data stream in response to determining that a first group of four octets of the identified eight octet sequence comprises a valid Core Header, and in response to determining that a second group of four octets of the identified eight octet sequence comprises one of a valid Core Header and a valid descrambled Type Header.