Abstract: The disclosure generally relates to a PCIe switch that includes a selectively transparent bridge that selectively allows transactions to traverse between multiple PCIe domains without the encumbrance of each root complex entity requiring knowledge of the selectively transparent bridge. The bridge that enables the transactions is invisible to the root complex entity in a host and drive switch domain of the PCIe switch. No address translation of the transactions is required because the drive switch domain address map is a subset of the host switch domain address map. The bridge allows for extremely low latency transactions between host systems and storage drives because the bridge allows the storage drive to read the Direct Memory Access (DMA) Scatter-Gather List (SGL) directly from host memory. The bridge also allows I/O data reads and writes from the storage drive directly to the host memory without store and forward within a RAID controller's memory.

Abstract: A method of measuring signal impairments is disclosed for use in an asynchronous Digital Signal Processing (DSP) based data and timing recovery circuit including an interpolator circuit. The method includes: calculating amplitude values for data and timing recovery; calculating an interpolation index for the interpolator circuit; and overriding the interpolation index. In another implementation, a method of measuring signal impairments in an asynchronous DSP-based data and timing recovery circuit including an interpolator circuit includes: calculating amplitude values for data and timing recovery; calculating a timing control signal; and overriding the timing control signal.

Abstract: A method and system for encoding ancillary information at a transmitter in a high-speed communications network, the method comprising: generating an electromagnetic interference (EMI) reduction signal; receiving an ancillary data symbol; generating an EMI reduction signal variation based on the ancillary data symbol; and varying a characteristic of the EMI reduction signal based on the generated EMI reduction signal variation to encode the ancillary data symbol in the varied EMI reduction signal.

Abstract: A data integrity (DI) protection circuit and method provide overlapping DI protection without increasing memory requirements. Write data parity is checked after write data error correcting code (ECC) check bits are generated, which is stored with the write data in memory without storing the write data parity. A corrupt location cache stores the write address and a write response error is generated when a write data parity error or write address parity error is detected. Read data and read data ECC check bits retrieved from the memory are checked and single bit errors are corrected, while double-bit errors result in a read error response. Read data parity is generated, and the corrected read data and corrected read data ECC check bits are then checked for bit errors. The corrupt location cache is searched for the read address, and a cache hit results in a read error response.

Abstract: A Forward Error Correction (FEC) decoder is provided, for example including a Layered Low Density Parity Check (LDPC) component. In an implementation, power consumption of the LDPC decoder is minimized with minimal to no impact on the error correction performance. This is achieved, in an implementation, by partially or fully eliminating redundant operations in the iterative process.

Abstract: A nonvolatile memory system and a method for using programming time to reduce bit errors in the nonvolatile memory system are disclosed. The method includes programming a plurality of memory cells of a nonvolatile memory device, identifying weak cells using programming time and preventing subsequent programming to the identified weak cells.