Abstract: A method for analyzing a target system that includes obtaining a plurality of characteristics from the target system using a characteristics extractor, wherein the plurality of characteristics is associated with a characteristics model, storing each of the plurality of characteristics in a characteristics store using a tracking mechanism, and analyzing the target system by issuing a query to the characteristics store to obtain an analysis result, wherein the query uses tracking information associated with the tracking mechanism.

Abstract: A method for analyzing a target system that includes obtaining a plurality of characteristics from the target system using a characteristics extractor, wherein the plurality of characteristics is associated with a characteristics model, storing each of the plurality of characteristics in a characteristics store, and analyzing the target system by issuing at least one query to the characteristics store to obtain an analysis result.

Abstract: A method for analyzing a target system that includes obtaining a characteristics model, loading the characteristics model into a meta model, obtaining a plurality of characteristics from the target system using a characteristics extractor, wherein each of the plurality of characteristics is associated with the characteristics model, storing each of the plurality of characteristics obtained from the target system in a characteristics store, and analyzing the target system by issuing at least one query to the characteristics store to obtain an analysis result, wherein the issuing the at least one query comprises verifying the at least one query using the meta model.

Abstract: A multi-stage switching network that can hitlessly reconfigure itself comprising a controller that controls each stage separately. The controller designates the paths through each stage according to the set of paths currently active. If the set of paths changes, the controller sends a new set of paths to the first stage while using the old set of paths for the second stage during a first frame. On the next frame, the controller causes both stages to use the new set of paths.

Abstract: A method for finding shortest paths is disclosed which uses a piecewise linear cost model to guide the search of through a compact tile graph and to ensure that a shortest path may always be found in a computationally effective manner. Cost function propagation from tile segment to tile segment is used to search for a target location from a source location through a region, and the shortest path is found through tracing backwards using the cost functions calculated during the searching. Linear minimal convolution is used to facilitate the cost function propagation.

Abstract: Method and apparatus for simultaneous optimization of the compiler to generate codes that may be compatible and acceptable for two or more different processors without potentially sacrificing the performance on any processors is provided. In particular, the rules of instructions scheduling for the machines of interest of different processors are abstracted. From the abstractions, a hypothetical machine is generated that is the restrictive or constraining set of the actual machines modeled in the abstraction step. After generating the hypothetical machine, the restricted hypothetical machine is targeted rather than the actual machines modeled in the first step. Thereafter, conflicts, if any are resolved by modeling the performance impact and selecting the less damaging choice.

Abstract: A multiply execution unit that is operable to generate the integer product and the XOR product of a multiplicand and a multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The partial products may be Booth encoded. The summing circuit can generate an integer sum of the plurality of partial products and can generate an XOR sum of the plurality of partial products. The summing circuit includes a first plurality of full adders. The first plurality of full adders each has three inputs, a carry output, and a sum output. The sum outputs of the first plurality of full adders are independent of the value of any carry output in the summing circuit. The summing circuit also includes a second plurality of full adders. The second plurality of full adders each has three inputs, a carry output, and a sum output.

Abstract: A system maintains a copy of data stored in a first memory device in a redundant distinct second memory device. Upon detecting an uncorrectable error in the first memory device, the system then relies on the copy of the data in the second memory device. The system, once it starts relying on the data in the second memory device, may then test the first memory device to determine if the uncorrectable error was due to a physical problem or a transient event. If the first memory device is then found to be working correctly, it may, in turn, become a redundant memory device for the second memory device.

Abstract: Disclosed are novel methods and apparatus for reorganizing data in a log file. In an embodiment, a method of reorganizing data in an original log file is disclosed. The method includes: obtaining a data record from the original log file; examining the data record; if the data record includes a single-value entry, inserting the data record in a single-value storage linked list; if the data record includes a multiple-values entry, inserting the data record in a multiple-values linked list; and utilizing data from the multiple-values and single-value linked lists to write data to a new log file.

Abstract: A distributed system provides for separate management of dynamic cluster membership and distributed data. Nodes of the distributed system may include a state manager and a topology manager. A state manager handles data access from the cluster. A topology manager handles changes to the dynamic cluster topology. The topology manager enables operation of the state manager by handling topology changes, such as new nodes to join the cluster and node members to exit the cluster. A topology manager may follow a static topology description when handling cluster topology changes. Data replication and recovery functions may be implemented, for example to provide high availability.

Abstract: In a system where client and server components (or actors) of an application are organized as complementary hierarchical graphs, a method and apparatus for creating server applications and dynamically deploying server applications on a client system are described. The server graph comprises, as a minimum, server nodes corresponding to the union of all possible client nodes, whereas each client graph corresponds to a subset of the related server nodes. The server graph is a compound tree from which all possible combinations of client trees can be dynamically created. At a desired time, for example, when the client requests for a client tree representation, the server creates the client tree representation using a peeling process to determine which nodes in the server actor tree should be included in the client tree representation. The peeling process involves determining the server actor nodes that meet a set of criteria for the particular client.

Abstract: Apparatus and methods for detecting passing magnetic articles including an offset adjustment circuit for adjusting the DC level of the magnetic field signal based on a dynamically adjustable offset threshold signal. The detector includes a PDAC for tracking the positive peaks of a magnetic field signal and an NDAC for tracking the negative peaks of the magnetic field signal. In one embodiment, the offset threshold signal includes a positive offset threshold signal and a negative offset threshold signal that are initially set at fixed respective signal levels and that become the level of the PDAC signal and NDAC signals, respectively, in response to a counter, that counts a number of increments of the PDAC signal and decrements of the NDAC signal, reaching a predetermined count value.

Abstract: A method and apparatus are disclosed for supplying power in electronic equipment. Thus the apparatus comprises at least one electronic component and a power supply unit that provides power to the electronic component. The power supply unit incorporates a detector that is responsive to the power output level from the power supply unit increasing beyond a predetermined limit. If this limit is breached, the power supply unit outputs a delay signal to the electronic component. This delay signal then causes the electronic component to reduce its power consumption (such as by performing dummy operations), thereby avoiding an overload on the power supply unit.

Abstract: A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data utilizing a corresponding received source synchronous clock signal, and transmit the recovered data and a corresponding clock signal in a source synchronous manner. In one embodiment, the device is configured to operate as a repeater without benefit of an internal clock signal. In addition, the device may be configured to remove data jitter and renew or restore amplitude to attenuated signals prior to retransmission.

Abstract: One embodiment of the present invention provides an arrangement of differential pairs of wires that carry differential signals across a semiconductor chip. In this arrangement, differential pairs of wires are organized within a set of parallel tracks on the semiconductor chip. Furthermore, differential pairs of wires are organized to be non-adjacent within the tracks. This means that each true wire is separated from its corresponding complement wire by at least one intervening wire in the set of parallel tracks, thereby reducing coupling capacitance between corresponding true and complement wires. Moreover, this arrangement may include one or more twisting structures, wherein a twisting structure twists a differential pair of wires so that the corresponding true and complement wires are interchanged within the set of parallel tracks.

Abstract: One embodiment of the present invention provides a system and method for providing a flexible framework for remote heterogeneous server management and control. A user interface framework is generated to export control and display features in a user interface effecting task execution and management of one or more remote heterogeneous agents responsive to user interaction. A management station framework is executed and includes services and base management functions implemented in management modules. The management station framework further generates the control and display features of the user interface and maintains a database storing management information. An agent framework provides execution of commands to control and return of results from one or more agents. The agent framework further includes an interface loading and accessing agent code located on one or more applications deployed to each agent.

Abstract: One embodiment of the present invention provides a system that performs a carry-save square root operation that calculates an approximation of a square root, Q, of a radicand, R. The system calculates Q by iteratively selecting an operation to perform based on higher-order bits of a remainder, r, and then performs the operation. This operation can include subtracting two times a square root calculated thus far, q, and a coefficient, c, from r, and adding c to q. During this operation, the system maintains r in carry-save form, which eliminates the need for carry propagation while updating r, thereby speeding up the square root operation. Furthermore, the selection logic, which decides what operation to perform next, is simpler than previous square-root implementations, thereby providing a further speedup.

Abstract: A method and system for inserting repeaters at different levels in a processor hierarchy involve tracing a net in a processor circuit followed by inserting repeaters at different locations in the net. The net is a circuit trace of wiring between circuit elements of a circuit, the net being divided into two nets. One net includes internal circuit elements of a processor component and another net includes external circuit elements of a processor component. A repeater solution, which includes inserted repeaters coupled to the internal circuit elements, is instantiated to other processor components. Subsequently, after instantiation of the repeater solution, repeaters are inserted in the nets external to the processor component.

Abstract: A garbage collector divides the garbage-collected heap into “cards.” It maintains a table containing a card-object table entry for each card. A card's entry contains information from which the collector can determine where any references in the card are located and thereby identify objects that may be reachable. The encoding of a card's table entry is not restricted to values that indicate the location of the object in which the card begins. Instead, its possible values additionally include ones that indicate that the card begins with a certain number of references or that an object begins at a given location in the middle of the card. The collector thereby avoids consulting object's class information unnecessarily.

Abstract: Operations including inserted prefetch operations that correspond to addressing chains may be scheduled above memory access operations that are likely-to-miss, thereby exploiting latency of the “martyred” likely-to-miss operations and improving execution performance of resulting code. More generally, certain pre-executable counterparts of likely-to-stall operations that form dependency chains may be scheduled above operations that are themselves likely-to-stall.