Abstract: A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic portion (108-0, 108-1) that receives the data stored therein. Memory areas and the logic portions of each memory/logic cell can be arranged on the substrate in a shape of an L, U, S, T, or Z to form a pair of interlocking memory/logic cells.

Abstract: A method of determining at least one ratio of transistor sizes. The method includes creating a sizing model by replacing at least one logic element in a circuit description with a sizing element that includes a piece-wise-linear current source. The method also includes determining a steady state solution to the sizing mode and determining at least one ratio of transistor sizes from the steady state solution. The method may also include determining at least one dimension of a transistor based at least in part upon the ratio of transistor sizes.

Abstract: A system for emulating a telematics client is provided. The system includes a workstation in communication with a display screen. A software stack configured to be executed by the workstation to implement functionality for a telematics client is included. The software stack imitates a configuration of an in-vehicle telematics stack of a telematics control unit (TCU). The software stack includes a service gateway for loading an emulator. A user interface (UI) manager configured to communicate with the loaded emulator is included with the software stack. The UI manager enables a presentation of TCU user interface without accessing the TCU. Methods to emulate a user interface and loading an emulator on a workstation are also provided.

Abstract: In some embodiments, an electronics assembly may include a frame with a motherboard and a plurality of daughterboards. The frame may have an opening opposite the motherboard to allow insertion of the daughterboards into the frame or removal of the daughterboards from the frame. An injector/ejector mechanism for each daughterboard may be located on the daughterboard or the frame. The frame may further include a flange that extends along the frame at or adjacent to the opening and on which the injector/ejector mechanism of each daughterboard is attached or engages at different locations along the length thereof. The flange may be divided into separate sections that correspond to the different locations to allow the flange to flex at any location along the frame during insertion of a daughterboard without the flexing affecting the position of any adjacent location of the flange with respect to the motherboard.

Abstract: A content addressable memory (CAM) device (200) can equalize a potential between a match line (202) and corresponding pseudo-supply (PVSS) line (204) in a pre-sense operation. In a sense operation, a sensing device (P4) can determine a match condition exists when the match line (202) potential varies from the PVSS line (204) potential. Complementary compare data lines (CD and BCD) can be equalized with one another in a pre-sense operation, while one compare data line (CD or BCD) can be equalized with bit lines (BB1 and/or BB2) in the sensing operation.

Abstract: A system and method of predicting network data traffic includes coupling a first group of clients to a current server that results in a current CPU utilization of the current server. A second group of clients are coupled to the current server. A load multiple is determined and the current CPU utilization is compared to a predicted CPU utilization. A server requirement is increased if the current CPU utilization is greater than or equal to the predicted CPU utilization.

Abstract: A fault tolerant computing system is provided comprising two or more processing sets that operate in synchronism with one another. The two processing sets are joined by a bridge, and there is a communications link for each processing set for transmitting data from the processing set to the bridge. Data transmissions are initiated in synchronism with one another from the respective processing sets to the bridge but are then subject to variable delay over the communications link. Accordingly, a buffer is included in the bridge for storing the data transmissions received from the processing sets for long enough to compensate for the variable delay. The data transmissions can then be fed out from the buffer to a comparator that verifies that the data transmissions received from the two or more processing sets properly match each other. Likewise, a buffer is included in each processing set for storing the data transmissions received from the bridge for long enough to compensate for the variable delay.

Abstract: Techniques for increasing the performance of virtual machines are disclosed. It can be determined whether a program instruction which is to be executed by the virtual machine is a branch instruction, and whether a basic block of code is present in a code cache. If so, the basic block of code can be executed. The basic block includes code that can be executed for the program instruction. A cache can be used to store the basic block for program instructions that are executed by the virtual machine. The program instruction may be a bytecode and the code cache can be implemented as a native code cache.

Abstract: According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operands and the second number of operands. The first source register includes a plurality of first operands and the destination register includes a plurality of results. The number of arithmetic processors are respectively coupled to the first operands, second operands and results, wherein each arithmetic processor computes one of a sum and a difference of the first operand and a respective second operand.

Abstract: One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation, the system receives a temporary result during execution of an in-flight instruction. Next, the system generates a parity bit for the temporary result, and stores the temporary result and the parity bit in a temporary register within the CPU. Before the temporary result is committed to the architectural state of the CPU, the system checks the temporary result and the parity bit to detect a bit error. If a bit error is detected, the system performs a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result. Otherwise, if a bit error is not detected, the system commits the temporary result to the architectural state of the CPU.

Abstract: A thin-client device broadcasts a configuration request message over a network. In response to the configuration request message, the thin-client device receives a configuration response message including a first set of configuration information. The thin-client device determines if the configuration response message includes a second set of configuration information. If the configuration response message does not include the second set of configuration information, the thin-client device broadcasts a status message over a network. In response to the status message, the thin-client device receives a status response message with the second set of configuration information.

Abstract: One embodiment of the present invention provides a system that supports directory-based cache coherence in an object-addressed memory hierarchy in a computer system. During operation, the system receives a cache-coherence transaction for a cache line. If the cache line is an object-addressed cache line, the system uses a corresponding object identifier and offset to look up directory information specifying where copies of the object-addressed cache line are located in the caches in the computer system. Next, the system uses the directory information to perform the cache-coherence transaction.

Abstract: The present invention provides a method and apparatus for capturing system error messages. The method includes accessing information associated with an error. The method further includes identifying a category associated with the error based upon the accessed information and accessing at least one pre-determined attribute in the accessed information based upon the identified category.

Abstract: The present invention relates to managing defunct processes. A parent process that does not collect exit information associated with a child process may leave a defunct child process. A defunct child process is identified. The parent process of the defunct child process is modified. The parent process can be modified by changing an existing thread or instantiating a new thread to collect exit information associated with the child process. Collecting exit information causes the removal of the defunct child process.

Abstract: A transparent proxy server is implemented by directing particular client packets to a proxy server that handles communications between the client and an origin server. When a client sends a packet to an origin server, a router transparently redirects the packet to the proxy server by storing the proxy server address in the destination field and the origin server address in the record route options field. The proxy server sends connection setup requests to the origin server and forwards acknowledgement packets to the client. For other requests, the proxy server determines whether the requested information is stored in the proxy server cache. If so, the information is retrieved from the cache; if not, the information is retrieved from the origin server. All acknowledgement and information packets are sent to the client with the origin server address in the source field, making it appear that the origin server sent the packets.

Abstract: A method and structure for equipping a cache with information to enable the processor to track and report whether a given speculative access causes prefetches and/or pollutions of the cache. Two types of events are tracked in one of two different ways: first by counting/tracking prefetch operations, either globally or on a per instruction address basis and then by counting/tracking cache pollutions, either globally or on a per instruction address basis.

Abstract: A method and apparatus to determine readiness of a complex instruction for retirement includes decoding a complex instruction into a plurality of helper instructions; executing the plurality of helper instructions using an execution unit; indicating the plurality of helper instructions that are alive using a live instruction register; and maintaining a complex instruction identification for the complex instruction using a complex instruction identification register.

Abstract: A method and apparatus for producing an enhanced CRL. In response to a request containing an identifier of the most recently owned CRL stored by the requested, a certificate authority generates a CRL spanning from the most recently owned CRL to the current CRL. This CRL is formatted as a delta CRL and transmitted as a reply to the requester. This has the advantage of not requiring transmission of the full CRL even though more than one generation of CRL has occurred since the most recently owned CRL by the requester.

Abstract: A computer system is provided having at least one processing resource, at least one power resource and at least one redundant power resource. The at least one processing resource is operable to exploit a greater level of power than is provided by the at least one power resource. The at least one processing resource is configured to exploit power provided by both the at least one power resource and the at least one redundant power resource, at a time when both the at least one power resource and the at least one redundant power resource are both operable to provide power.

Abstract: A system for automatically encrypting and decrypting data packet sent from a source host to a destination host across a public internetwork. A tunnelling bridge is positioned at each network, and intercepts all packets transmitted to or from its associated network. The tunnelling bridge includes tables indicated pairs of hosts or pairs of networks between which packets should be encrypted. When a packet is transmitted from a first host, the tunnelling bridge of that host's network intercepts the packet, and determines from its header information whether packets from that host that are directed to the specified destination host should be encrypted; or, alternatively, whether packets from the source host's network that are directed to the destination host's network should be encrypted.