Abstract: A radio system comprises a front-end receiver for receiving a RF signal and converting the RF signal into a digital payload signal. The system further comprises a base-band processor for processing the digital payload signal, and a serial data interface over which the front-end communicates the digital payload signal and meta data to the base-band processor. The meta data may comprise information indicating whether a corresponding digital payload signal communicated over the serial data interface is valid and additional information of the front-end status, e.g. gain or state of tuning.

Abstract: Systems and methods which provide for reduced intra communication system information transfer by providing a compressed representation of a portion of intra communication system information are shown. An embodiment operates to provide intra communication system transfer of uncompressed received information while providing intra communication system transfer of a compressed representation of information ancillary to the received information. According to embodiments, ancillary information, such as CSI, associated with other transferred information is transferred with reduced data throughput requirements through application of compression techniques with respect to the transferred ancillary information. Embodiments additionally or alternatively reduce the intra communication system information transferred by reducing the received information transferred.

Abstract: When dynamically varying a number of active paths in a system, a desired return loss is maintained. Certain embodiments enable dynamic varying of the impedance of parallel signal paths in a system responsive to the number of active ones of the parallel paths dynamically changing, in order to maintain a relatively constant impedance match between a source and the combination of parallel paths, thereby retaining a desired return loss.

Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

Abstract: A system includes a filter and a tuner formed on an integrated circuit. The filter receives an input signal comprising a first number of channels and communicates an intermediate output signal comprising a second number of channels less than the first number of channels. The tuner is coupled to the filter and receives the intermediate output signal and communicates an output signal comprising a third number of channels less than the second number of channels.

Abstract: A circuit includes a first filter comprising a first inductor coupled to a first variable capacitor, wherein the first filter is associated with a first resonant frequency. The circuit further comprises an amplifier coupled to the first filter and a second filter coupled to the amplifier. The second filter comprises a second inductor coupled to a second variable capacitor, wherein the second filter is associated with a second resonant frequency that is substantially the same as the first resonant frequency. At least a portion of the first filter and at least a portion of the second filter are formed on an integrated circuit.

Abstract: An attenuator system includes a first adjustable impedance component on a first current path between a input component and a output component, and a second adjustable impedance component between the first current path and ground, wherein each of the first and second adjustable impedance components include a plurality of selectable, discrete legs, each leg having an impedance.

Abstract: A system for providing automatic gain control (AGC) comprises a signal path with an RF input, a plurality of power detectors in communication with the signal path, each of the power detectors operable to measure a total broadband power level of a signal in the signal path, each of the power detectors positioned to monitor a point in the signal path corresponding to a change in signal bandwidth, a control system operable to receive from each of the power detectors information associated with the power level and to adjust attenuation in the signal path in response to the information to achieve desired gain control.

Abstract: A circuit includes a first filter comprising a first inductor coupled to a first variable capacitor, wherein the first filter is associated with a first resonant frequency. The circuit further comprises an amplifier coupled to the first filter and a second filter coupled to the amplifier. The second filter comprises a second inductor coupled to a second variable capacitor, wherein the second filter is associated with a second resonant frequency that is substantially the same as the first resonant frequency. At least a portion of the first filter and at least a portion of the second filter are formed on an integrated circuit.

Abstract: In one embodiment of the present invention, a dynamic multi-path detection device is disclosed to include at least one narrow-band signal metric estimator responsive to input signal. Each of the at least one estimators measures a particular characteristic of the input signal in a frequency band that is narrower than the overall signal bandwidth and is operative to generate a signal parameter estimate signal. The dynamic multi-path detection device is further disclosed to include a signal metric comparison device responsive to the signal parameter estimate signal(s) and operative to generate a dynamic multi-path indication signal for detecting dynamic multi-path.

Abstract: A digital radio system comprises a mixer and an analog-to-digital converter communicative coupled to the mixer. The mixer generates an intermediate frequency signal based at least in part upon a radio frequency signal and a local oscillator signal, wherein the intermediate frequency signal comprises a signal of interest having a particular bandwidth. The analog-to-digital converter generates a digital signal by quantizing the intermediate frequency signal using a sampling frequency that is greater than twice the bandwidth of the signal of interest and less than the frequency of the intermediate frequency signal.

Abstract: A broadband integrated receiver for receiving input signals and outputting composite video and audio signals is disclosed. The receiver employs an up-conversion mixer and a down-conversion mixer in series to produce an intermediate signal. An intermediate filter between the mixers performs coarse channel selection. The down-conversion mixer may be an image rejection mixer to provide additional filtering.

Abstract: A system for processing signals comprises a tuner and an input/output (IO) bus bridge, wherein the tuner and the IO bus bridge are formed at least in part on same semiconductor chip, and wherein at least a portion of logic on the chip is implemented in Complementary Metal Oxide Semiconductor (CMOS) logic, and wherein at least another portion of the logic is implemented with silicon germanium (SiGe) logic.

Abstract: A system for tuning an impedance at a node comprises a first component associated with a first impedance when the first component is operating and a second impedance when the first component is not operating. The system further comprises a second component coupled to the first component at a node. The second component is associated with a third impedance when the second component is operating and a fourth impedance when the second component is not operating. An impedance tuning circuit is coupled to the second component at the node and operable to tune an impedance at the node based at least in part upon a plurality of the first impedance, the second impedance, the third impedance, and the fourth impedance.

Abstract: Disclosed are systems and methods of eliminating or reducing interference resulting from harmonics of local oscillator frequencies of mixers. In one embodiment, a determination is made as to a zone or zones in which harmonics result in undesired spur generation. Inter-tuner spurs and intra-tuner spurs may be identified such that frequency information of the identified spurs may be utilized to define a plurality of exclusion zones. LO frequencies may subsequently be efficiently selected in view of the exclusion zone information. Embodiments may also determine a score for identified spurs which may be used to optimally select from within a set of spur-generating local oscillator frequencies.

Abstract: A broadband signal amplifier includes one of more broadband amplifier circuits, each dynamically controlled in response to a total power level of signals applied thereto to reduce linearity in response to a reduction of input signal strength. A filter may couple the output of the broadband amplifier circuits to each other to form a tandem arrangement. Power detectors are connected to detect and provide outputs indicative of the total power levels of the signals applied to respective broadband amplifiers. A control unit is connected to and receives the output from the power detectors and, in response, provides a control signals to the broadband amplifier circuit so as to operate each over portions of their operating characteristic curves that provide only that degree of linearity necessary to limit distortion to a predetermined or dynamically adjustable maximum acceptable level.

Abstract: The present invention is directed to a system and method of reducing frequency interference in a circuit when the harmonics of at least two frequencies could cause interference when such harmonics interact with each other. In one embodiment, a determination is made as to which harmonic could possibly support such interference, and based upon the determined harmonic, determining which combination within said determined harmonic is likely to cause the interference.

Abstract: In one embodiment of the present invention, a segmented equalizer includes a plurality of feedforward equalizer segments, each feedforward equalizer segment responsive to delayed samples of an input signal {vn}, wherein n is the index of samples, and including a filter block for filtering the delayed samples by using coefficients which are updated based on a step size generated for each equalizer segment.

Abstract: A device for measuring voltage levels includes a root mean square (RMS) detector. The RMS detector includes a linear multiplier, a log converter, a low-pass filter and a temperature compensator. The linear multiplier multiplies a voltage of an input signal by the voltage of the input signal. The low-pass filter couples to an output of the linear multiplier. The log converter generates a logarithmic signal having a voltage that is logarithmically related to a voltage of an output of the low-pass filter. The temperature compensator adjusts the logarithmic signal based on a temperature of the RMS detector. The RMS detector is capable of determine an RMS voltage level of the input signal.