Abstract: Frequency translation, such as frequency up conversion of a video baseband or intermediate frequency to a desired frequency division broadcast channel, is provided utilizing a single sideband or image reject mixer and filtering having relaxed selectivity requirements. According to a preferred embodiment, a first single sideband mixer accepts an input signal at an intermediate frequency and up converts this signal to a high intermediate frequency. The image rejection provided by the single sideband mixer in combination with simple filtering provide sufficient signal quality to achieve desired levels of desired signal isolation, such as on the order of 40 dB. Preferably, a second single sideband mixer accepts the high intermediate frequency signal and down converts this signal to a desired transmission or broadcast frequency.

Abstract: A circuit for frequency translating a radio frequency signal comprises a plurality of mixer stages, each stage associated with a particular range of frequencies of a radio frequency signal. The circuit further comprises a switching circuit that communicates the radio frequency signal to a selected one of the plurality of mixer stages in response to a control signal. The selected mixer stage comprises a phase generation circuit that generates a plurality of phase signals, and at least one mixer that combines the radio frequency signal with one of the plurality of phase signals to generate at least a portion of an intermediate frequency signal.

Abstract: Disclosed are systems and methods which provide phase shifting of signals while minimizing signal attenuation associated with providing such phase shifting. Preferred embodiments provide a compact polyphase filter structure in which the geometry of the polyphase filter both minimizes parasitic capacitance and signal transmission paths therein. A polyphase filter of a preferred embodiment utilizes a radial pinwheel structure providing a geometry in which successive circuit components are disposed very near one another and in an orientation to accommodate very short connections therebetween. Embodiments may include the use of a buffer at the outputs of the polyphase filter circuit to reduce the amount of parasitics associated with the polyphase filter.

Abstract: A method and apparatus for tuning a VCO circuit to provide desired modulations is described. In one embodiment, the method of the present invention uses a controlled voltage from a digital-to-analog converter to obtain VCO voltage/frequency characteristics. The VCO voltage/frequency characteristics are used to determine a VCO capacitance value as well as a charge pump current level for each frequency band of interest. For one embodiment, the VCO circuit includes a bank of switchable capacitors used to set the VCO capacitance value. The charge pump includes a number of switch-controlled current meters to set the charge pump current level. The VCO capacitors and charge pump current meters are controlled by an off-chip CPU.

Abstract: Frequency translation, such as frequency up conversion of a video baseband or intermediate frequency to a desired frequency division broadcast channel, is provided utilizing a single sideband or image reject mixer and filtering having relaxed selectivity requirements. According to a preferred embodiment, a first single sideband mixer accepts an input signal at an intermediate frequency and up converts this signal to a high intermediate frequency. The image rejection provided by the single sideband mixer in combination with simple filtering provide sufficient signal quality to achieve desired levels of desired signal isolation, such as on the order of 40 dB. Preferably, a second single sideband mixer accepts the high intermediate frequency signal and down converts this signal to a desired transmission or broadcast frequency.

Abstract: A circuit and method for adjusting the operating characteristics of a tuner in accordance with information derived from the signals being processed by the tuner. Depending upon signal type and/or signal strength, the power levels of certain components are adjusted and/or certain components are added to (or subtracted from) the tuner.

Abstract: A method for generating phase signals includes triggering a phase register to output a binary number stored in the phase register, wherein the phase register is triggered based at least in part on a voltage signal provided by a voltage controlled oscillator. The method also includes providing an input signal to a decoder, wherein the input signal is based at least in part on the binary number output by the phase register and the decoder is operable to generate phase signals in response to the input signals. The method further includes incrementing the binary number stored in the phase register and repeating the triggering and providing steps after the binary number is incremented.

Abstract: In one embodiment, a system for automatically establishing a wireless connection between adapters includes a master adapter coupleable to a peripheral device. The master adapter can automatically enter an inquiry mode in response to the occurrence of a first event. In the inquiry mode, the master adapter automatically establishes one or more wireless connections between the master adapter and one or more slave adapters that are coupled to one or more computer systems. The master adapter can also automatically enter an operational mode in response to the occurrence of a second event. In the operational mode, the master adapter enables communication between the peripheral device and the one or more computer systems via the one or more wireless connections using a wireless protocol.

Abstract: Systems and methods which implement calibration for signal errors in a communication network, such as non-uniform frequency response, are disclosed. According to a preferred embodiment of the invention, a calibration signal is communicated through the network and a receiver at a subscriber premises operates to calibrate the received signal for any tilt introduced in the signal path between the source of the signal and the subscriber premises. Preferred embodiments of the present invention provide for monitoring of the performance of signal correction components, such as by providing a feedback path from the receiver. Monitoring of calibration performance may be utilized according to preferred embodiments for developing a more full understanding of the operation of the network, identify sources of network problems, and even predict system degradation and take appropriate action before service interruption results.

Abstract: A broadband integrated receiver for receiving input signals and outputting composite video and audio signals is disclosed. The receiver employs an up-conversion mixer and a down-conversion mixer in series to produce an intermediate signal. An intermediate filter between the mixers performs coarse channel selection. The down-conversion mixer may be an image rejection mixer to provide additional filtering.

Abstract: A broadband integrated receiver for receiving input signals and outputting composite video and audio signals is disclosed. The receiver employs an up-conversion mixer and a down-conversion mixer in series to produce an intermediate signal. An intermediate filter between the mixers performs coarse channel selection. The down-conversion mixer may be an image rejection mixer to provide additional filtering.

Abstract: A method for storing a result of a tuning process includes generating a first characteristic signal using a signal generator. The method also includes generating a second characteristic signal using a master circuit, wherein the master circuit generates the second characteristic signal in response to a current signal. The method further includes determining an adjustment to the current signal based at least in part upon the first and second characteristic signals, and storing a digital value representing the adjustment.

Abstract: A system is described comprising: a finite state machine having a plurality of states interconnected through a plurality of events, wherein certain states and events in said plurality are implemented in software and other states and events in said plurality are implemented in hardware; and a scheduler communicatively coupled to the finite state machine and being programmable with one or more parameters defining scheduled operations to be performed by the scheduler, wherein the finite state machine is configured to select one or more of said parameters to be used by said scheduler upon transition by said finite state machine from a first state to a second state.

Abstract: An apparatus and methods for concealing missing packets in a CVSD bit stream are disclosed. In one embodiment, an indication from a packet loss indicator (PLI) that a packet is missing is received. Next the status of the missing packet is determined. Based on the status of the missing packet, a sample packet is generated to replace the missing packet, and a memory of the CVSD is updated. A compressed copy of the sample packet may be stored in a first memory buffer in either ?-law or a-law format.

Abstract: The present invention is directed to a system and method of reducing frequency interference in a circuit when the harmonics of at least two frequencies could cause interference when such harmonics interact with each other. In one embodiment, a determination is made as to which harmonic could possibly support such interference, and based upon the determined harmonic, determining which combination within said determined harmonic is likely to cause the interference.

Abstract: A cable receiver system and method which utilizes the combination of time-division multiplexing (“TDM”) and a fast-acquisition-time tuner to enable on/off pulsing of the tuner, thereby resulting in substantially reduced power consumption by the tuner. The tuner may be pulsed on during the allocated time slot to receive the allocated portion of the signal, and then pulsed off the remainder of the time. The tuner generally requires a fast signal acquisition time compared to the received signal's frame rate so that the tuner does not use up an excess amount of the frame outside of the proper time slot when locking in the received signal. The TDM technique permits more efficient use of the high bandwidth network by multiplexing the relatively low bandwidth voice signals. In addition, the implementation of a fast-acquisition-time tuner in the NIU of a cable system permits the tuner to be pulsed off for a substantial amount of the time between the allocated time slots.

Abstract: The present invention is directed to a system and method of reducing frequency interference in a circuit when the harmonics of at least two frequencies could cause interference when such harmonics interact with each other. In one embodiment, a determination is made as to which harmonic could possibly support such interference, and based upon the determined harmonic, determining which combination within said determined harmonic is likely to cause the interference.

Abstract: Disclosed are systems and methods of eliminating or reducing interference resulting from harmonics of local oscillator frequencies of mixers. In one embodiment, a determination is made as to a zone or zones in which harmonics result in undesired spur generation. Inter-tuner spurs and intra-tuner spurs may be identified such that frequency information of the identified spurs may be utilized to define a plurality of exclusion zones. LO frequencies may subsequently be efficiently selected in view of the exclusion zone information. Embodiments may also determine a score for identified spurs which may be used to optimally select from within a set of spur-generating local oscillator frequencies.

Abstract: A filter circuit includes a polyphase filter coupled to a first circuit component and a second circuit component. The first circuit component propagates four input current signals to the polyphase filter. The third and fourth input current signals are substantially one-hundred-eighty degrees out of phase with the first and second input current signals. The polyphase filter receives the input current signals and generates four output current signals that are out of phase with each other. The second circuit component generates first and second output signals using the four output current signals. The first and second output signals are ninety degrees out of phase with each other.

Abstract: Linearizer circuitry is disclosed for providing control signal outputs to operate a controllable attenuator throughout a relatively large dynamic range while maintaining a relatively consistent return loss. Preferred embodiment linearizer circuitry provides a series control current and a shunt control current for coupling to a PIN diode attenuator, such as may be configured in a ? network or a T network. Preferably, differential pairs are utilized in providing each of the control current outputs.